Struct imxrt_hal::lpspi::Transaction

pub struct Transaction {
    pub byte_swap: bool,
    pub bit_order: BitOrder,
    pub receive_data_mask: bool,
    pub transmit_data_mask: bool,
    pub continuous: bool,
    pub continuing: bool,
    /* private fields */
}

An LPSPI transaction definition.

The transaction defines how many bits the driver sends or recieves. It also describes

• endianness
• bit order
• transmit and receive masking
• continuous and continuing transfers (default: both disabled)

The LPSPI enqueues the transaction data into the transmit FIFO. When it pops the values from the FIFO, the values take effect immediately. This may affect, or abort, any ongoing transactions. Consult the reference manual to understand when you should enqueue transaction definitions, since it may only be supported on word / frame boundaries.

Construct Transaction with new, and supply the number of bits to transmit per frame.

use imxrt_hal as hal;
use hal::lpspi::Transaction;

// Send one u32.
let mut transaction
    = Transaction::new(8 * core::mem::size_of::<u32>() as u16);

Once constructed, manipulate the public members to change the configuration.

Continuous transactions

The pseudo-code below shows how to set continuous and continuing to model a continuous transaction. Keep in mind the hardware limitations; see the module-level docs for details.

use imxrt_hal as hal;
use hal::lpspi::Transaction;

// Skipping LPSPI initialization; see module-level example.

// Start byte exchange as a continuous transaction. Each frame
// exchanges one byte (eight bits) with a device.
let mut transaction = Transaction::new(8)?;
transaction.continuous = true;
// Enqueue transaction with LPSPI...
// Enqueue one byte with LPSPI...   <-- PCS asserts here.

for byte in buffer {
    // Set 'continuing' to indicate that the next
    // transaction continues the previous one...
    transaction.continuing = true;

    // Enqueue transaction with LPSPI...
    // Enqueue byte with LPSPI...
}

transaction.continuous = false;
transaction.continuing = false;
// Enqueue transaction with LPSPI... <-- PCS de-asserts here.

Fields

byte_swap: bool

Enable byte swap.

When enabled (true), swap bytes with the u32 word. This allows you to change the endianness of the 32-bit word transfer. The default is false.

bit_order: BitOrder

Bit order.

See BitOrder for details. The default is BitOrder::Msb.

receive_data_mask: bool

Mask the received data.

If true, the peripheral discards received data. Use this when you only care about sending data. The default is false; the peripheral puts received data in the receive FIFO.

transmit_data_mask: bool

Mask the transmit data.

If true, the peripheral doesn’t send any data. Use this when you only care about receiving data. The default is false; the peripheral expects to send data using the transmit FIFO.

continuous: bool

Indicates (true) the start of a continuous transfer.

If set, the peripherals chip select will remain asserted after exchanging the frame. This allows you to enqueue new commands and data words within the same transaction. Those new commands should have continuing set to true.

The default is false; chip select de-asserts after exchanging the frame. To stop a continuous transfer, enqueue a new Transaction in which this flag, and continuing, is false.

continuing: bool

Indicates (true) that this command belongs to a previous transaction.

Set this to indicate that this new Transaction belongs to a previous Transaction, one that had continuous set. The default value is false.

Implementations

impl Transaction

pub fn new_u32s(data: &[u32]) -> Result<Self, LpspiError>

Defines a transaction for a u32 buffer.

After successfully defining a transaction of this buffer, supply it to the LPSPI driver, then start sending the data.

Returns an error if any are true:

• the buffer is empty.
• there’s more than 128 elements in the buffer.

pub fn new(frame_size: u16) -> Result<Self, LpspiError>

Define a transaction by specifying the frame size, in bits.

The frame size describes the number of bits that will be transferred and received during the next transaction. Specifically, it describes the number of bits for which the PCS pin signals a transaction.

Requirements

• frame_size fits within 12 bits; the implementation enforces this maximum value.
• The minimum value for frame_size is 8; the implementation enforces this minimum value.