imxrt_dma/ral/
tcd.rs

1//! Transfer Control Descriptor
2
3#![allow(non_snake_case, non_upper_case_globals, clippy::module_inception)]
4
5use super::RWRegister;
6
7/// DMA Transfer Control Descriptor (TCD)
8#[repr(C, align(32))]
9pub struct RegisterBlock {
10    pub SADDR: RWRegister<u32>,
11    // Signed numbers for offsets / 'last' members intentional.
12    // The hardware treats them as signed numbers.
13    pub SOFF: RWRegister<i16>,
14    pub DATTR: RWRegister<u8>,
15    pub SATTR: RWRegister<u8>,
16    pub NBYTES: RWRegister<u32>,
17    pub SLAST: RWRegister<i32>,
18    pub DADDR: RWRegister<u32>,
19    pub DOFF: RWRegister<i16>,
20    pub CITER: RWRegister<u16>,
21    pub DLAST_SGA: RWRegister<i32>,
22    pub CSR: RWRegister<u16>,
23    pub BITER: RWRegister<u16>,
24}
25
26const _STATIC_ASSERT_TCD_32_BYTES: [u32; 1] =
27    [0; (32 == core::mem::size_of::<RegisterBlock>()) as usize];
28
29impl RegisterBlock {
30    /// TCDs are uninitialized after reset. Set them to a known,
31    /// good state here.
32    pub fn reset(&self) {
33        self.SADDR.write(0);
34        self.SOFF.write(0);
35        self.DATTR.write(0);
36        self.SATTR.write(0);
37        self.NBYTES.write(0);
38        self.SLAST.write(0);
39        self.DADDR.write(0);
40        self.DOFF.write(0);
41        self.CITER.write(0);
42        self.DLAST_SGA.write(0);
43        self.CSR.write(0);
44        self.BITER.write(0);
45    }
46}
47
48mod ATTR {
49    /// Destination data transfer size
50    pub mod SIZE {
51        /// Offset (0 bits)
52        pub const offset: u8 = 0;
53        /// Mask (3 bits: 0b111 << 0)
54        pub const mask: u8 = 0b111 << offset;
55        /// Read-only values (empty)
56        pub mod R {}
57        /// Write-only values (empty)
58        pub mod W {}
59        /// Read-write values (empty)
60        pub mod RW {}
61    }
62
63    /// Destination Address Modulo
64    pub mod MOD {
65        /// Offset (3 bits)
66        pub const offset: u8 = 3;
67        /// Mask (5 bits: 0b11111 << 3)
68        pub const mask: u8 = 0b11111 << offset;
69        /// Read-only values (empty)
70        pub mod R {}
71        /// Write-only values (empty)
72        pub mod W {}
73        /// Read-write values (empty)
74        pub mod RW {}
75    }
76}
77
78pub mod DATTR {
79    pub use super::ATTR::*;
80}
81
82pub mod SATTR {
83    pub use super::ATTR::*;
84}
85
86pub mod CSR {
87
88    /// Enable an interrupt when major iteration count completes.
89    pub mod INTMAJOR {
90        /// Offset (1 bits)
91        pub const offset: u16 = 1;
92        /// Mask (1 bit: 1 << 1)
93        pub const mask: u16 = 1 << offset;
94        /// Read-only values (empty)
95        pub mod R {}
96        /// Write-only values (empty)
97        pub mod W {}
98        /// Read-write values
99        pub mod RW {}
100    }
101
102    /// Disable Request
103    pub mod DREQ {
104        /// Offset (3 bits)
105        pub const offset: u16 = 3;
106        /// Mask (1 bit: 1 << 3)
107        pub const mask: u16 = 1 << offset;
108        /// Read-only values (empty)
109        pub mod R {}
110        /// Write-only values (empty)
111        pub mod W {}
112        /// Read-write values
113        pub mod RW {}
114    }
115
116    /// Channel Done
117    pub mod DONE {
118        /// Offset (7 bits)
119        pub const offset: u16 = 7;
120        /// Mask (1 bit: 1 << 7)
121        pub const mask: u16 = 1 << offset;
122        /// Read-only values (empty)
123        pub mod R {}
124        /// Write-only values (empty)
125        pub mod W {}
126        /// Read-write values (empty)
127        pub mod RW {}
128    }
129
130    /// Bandwidth Control
131    pub mod BWC {
132        /// Offset (14 bits)
133        pub const offset: u16 = 14;
134        /// Mask (2 bits: 0b11 << 14)
135        pub const mask: u16 = 0b11 << offset;
136        /// Read-only values (empty)
137        pub mod R {}
138        /// Write-only values (empty)
139        pub mod W {}
140        /// Read-write values
141        pub mod RW {
142
143            /// 0b00: No eDMA engine stalls.
144            pub const BWC_0: u16 = 0b00;
145
146            /// 0b10: eDMA engine stalls for 4 cycles after each R/W.
147            pub const BWC_2: u16 = 0b10;
148
149            /// 0b11: eDMA engine stalls for 8 cycles after each R/W.
150            pub const BWC_3: u16 = 0b11;
151        }
152    }
153
154    /// Channel Active
155    pub mod ACTIVE {
156        /// Offset (6 bits)
157        pub const offset: u16 = 6;
158        /// Mask (1 bit: 1 << 6)
159        pub const mask: u16 = 1 << offset;
160        /// Read-only values (empty)
161        pub mod R {}
162        /// Write-only values (empty)
163        pub mod W {}
164        /// Read-write values (empty)
165        pub mod RW {}
166    }
167}
168
169pub mod CITER {
170    /// Current Major Iteration Count
171    pub mod CITER {
172        pub const offset: u16 = 0;
173        pub const mask: u16 = 0x7fff << offset;
174        pub mod R {}
175        pub mod W {}
176        pub mod RW {}
177    }
178}
179
180pub mod BITER {
181    /// Starting Major Iteration Count
182    pub mod BITER {
183        pub const offset: u16 = 0;
184        pub const mask: u16 = 0x7fff << offset;
185        pub mod R {}
186        pub mod W {}
187        pub mod RW {}
188    }
189}
190
191/// Throttles the amount of bus bandwidth consumed by the eDMA
192///
193/// Defines the number of stalls that the DMA engine will insert
194/// between most element transfers.
195///
196/// Some stalls may not occur to minimize startup latency. See the
197/// reference manual for more details.
198#[derive(Debug, Clone, Copy, PartialEq, Eq)]
199#[repr(u16)]
200pub enum BandwidthControl {
201    /// DMA engine stalls for 4 cycles after each R/W.
202    Stall4Cycles = CSR::BWC::RW::BWC_2,
203    /// DMA engine stalls for 8 cycles after each R/W.
204    Stall8Cycles = CSR::BWC::RW::BWC_3,
205}
206
207impl BandwidthControl {
208    pub(crate) fn raw(bwc: Option<Self>) -> u16 {
209        match bwc {
210            None => CSR::BWC::RW::BWC_0,
211            Some(bwc) => bwc as u16,
212        }
213    }
214}
imxrt_dma/ral/tcd.rs

imxrt_dma/ral/
tcd.rs
