Struct imxrt_dma::channel::Channel

pub struct Channel { /* private fields */ }

A DMA channel

You should rely on your HAL to allocate Channels. If your HAL does not allocate channels, or if you’re desigining the HAL, use Dma to create channels.

The Channel stores memory addresses independent of the memory lifetime. You must make sure that the channel’s state is valid before enabling a transfer!

Implementations

impl Channel

pub unsafe fn enable(&self)

Enable the DMA channel for transfers

Safety

enable() allows the DMA controller to read and write from the memory addresses stored in the channel. This is very unsafe:

• you must ensure that the lifetime of all memory is greater than the lifetime of the transfer
• you must ensure that no one else is using this channel for anything else
• if the transfer uses a circular buffer, you must ensure that the circular buffer is correctly sized and aligned.

pub fn channel(&self) -> usize

Returns the DMA channel number

Channels are unique and numbered within the half-open range [0, 32).

pub fn set_bandwidth_control(&mut self, bandwidth: Option<BandwidthControl>)

Set the channel’s bandwidth control

• None disables bandwidth control (default setting)
• Some(bwc) sets the bandwidth control to bwc

pub fn reset(&mut self)

Reset the transfer control descriptor owned by the DMA channel

reset should be called during channel initialization to put the channel into a known, good state.

pub unsafe fn set_source_address<E: Element>(&self, saddr: *const E)

Set the source address for a DMA transfer

saddr should be a memory location that can provide the DMA controller with data.

Safety

If the DMA channel is already enabled, the DMA engine may start reading this memory location. You must ensure that reads to saddr do not perform inappropriate side effects. You must ensure saddr is valid for the lifetime of the transfer.

pub unsafe fn set_source_offset(&self, offset: i16)

Set the source offset in bytes

offset could be negative, which would decrement the address.

Safety

This method could allow a DMA engine to read beyond a buffer or address. You must ensure that the source is valid for these offsets.

pub unsafe fn set_destination_address<E: Element>(&self, daddr: *const E)

Set the destination address for a DMA transfer

daddr should be a memory location that can store data from the DMA controller.

Safety

If the DMA channel is already enabled, the DMA engine may start writing to this address. You must ensure that writes to daddr are safe, and that the memory is valid for the lifetime of the transfer.

pub unsafe fn set_destination_offset(&self, offset: i16)

Set the destination offset in bytes

offset could be negative, which would decrement the address.

Safety

This method could allow a DMA engine to write beyond the range of a buffer. You must ensure that the destination is valid for these offsets.

pub unsafe fn set_source_attributes<E: Element>(&self, modulo: u8)

Set the transfer attributes for the source

Safety

An incorrect modulo value may allow the DMA engine to loop back to an incorrect address. You must ensure that modulo is valid for your source.

pub unsafe fn set_source_last_address_adjustment(&self, adjustment: i32)

Set the source last address adjustment in bytes

Safety

This could allow the DMA engine to reference an invalid source buffer. You must ensure that the adjustment performed by the DMA engine is valid, assuming that another DMA transfer immediately runs after the current transfer completes.

pub unsafe fn set_destination_last_address_adjustment(&self, adjustment: i32)

Set the destination last addrss adjustment in bytes

Safety

This could allow the DMA engine to reference an invalid destination address. You must ensure that the adjustment performed by the DMA engine is valid, assuming that another DMA transfer immediately runs after the current transfer completes.

pub unsafe fn set_destination_attributes<E: Element>(&self, modulo: u8)

Set the transfer attributes for the destination

Safety

An incorrect modulo value may allow the DMA engine to loop back to an incorrect address. You must ensure that modulo is valid for your destination.

pub unsafe fn set_minor_loop_bytes(&self, nbytes: u32)

Set the number of bytes to transfer per minor loop

Describes how many bytes we should transfer for each DMA service request. Note that nbytes of 0 is interpreted as a 4GB transfer.

Safety

This might allow the DMA engine to read beyond the source, or write beyond the destination. Caller must ensure that the number of bytes per minor loop is valid for the given transfer.

pub unsafe fn set_transfer_iterations(&mut self, iterations: u16)

Tells the DMA channel how many transfer iterations to perform

A ‘transfer iteration’ is a read from a source, and a write to a destination, with read and write sizes described by a minor loop. Each iteration requires a DMA service request, either from hardware or from software. The maximum number of iterations is 2^15.

Safety

This may allow the DMA engine to read beyond the source, or write beyond the destination. Caller must ensure that the number of iterations is valid for the transfer.

pub fn beginning_transfer_iterations(&self) -> u16

Returns the beginning transfer iterations setting for the channel.

This reflects the last call to set_transfer_iterations.

pub fn set_channel_configuration(&mut self, configuration: Configuration)

Set the DMAMUX channel configuration

See the Configuration documentation for more information.

Panics

Only the first four DMA channels support periodic triggering from PIT timers. This method panics if triggering is set for the Enable variant, but the channel does not support triggering.

pub fn is_hardware_signaling(&self) -> bool

Returns true if the DMA channel is receiving a service signal from hardware

pub fn disable(&self)

Disable the DMA channel, preventing any DMA transfers

pub fn is_interrupt(&self) -> bool

Returns true if this DMA channel generated an interrupt

pub fn clear_interrupt(&self)

Clear the interrupt flag from this DMA channel

pub fn set_disable_on_completion(&mut self, dreq: bool)

Enable or disable ‘disable on completion’

‘Disable on completion’ lets the DMA channel automatically clear the request signal when it completes a transfer.

pub fn set_interrupt_on_completion(&mut self, intr: bool)

Enable or disable interrupt generation when the transfer completes

You’re responsible for registering your interrupt handler.

pub fn is_complete(&self) -> bool

Indicates if the DMA transfer has completed

pub fn clear_complete(&self)

Clears completion indication

pub fn is_error(&self) -> bool

Indicates if the DMA channel is in an error state

pub fn clear_error(&self)

Clears the error flag

pub fn is_active(&self) -> bool

Indicates if this DMA channel is actively transferring data

pub fn is_enabled(&self) -> bool

Indicates if this DMA channel is enabled

pub fn error_status(&self) -> Error

Returns the value from the global error status register

It may reflect the last channel that produced an error, and that may not be related to this channel.

pub fn start(&self)

Start a DMA transfer

start() should be used to request service from the DMA controller. It’s necessary for in-memory DMA transfers. Do not use it for hardware-initiated DMA transfers. DMA transfers that involve hardware will rely on the hardware to request DMA service.

Flag is automatically cleared by hardware after it’s asserted.

Trait Implementations

impl Send for Channel