Enum iced_x86::OpCodeOperandKind

#[non_exhaustive]
pub enum OpCodeOperandKind {
    None = 0,
    farbr2_2 = 1,
    farbr4_2 = 2,
    mem_offs = 3,
    mem = 4,
    mem_mpx = 5,
    mem_mib = 6,
    mem_vsib32x = 7,
    mem_vsib64x = 8,
    mem_vsib32y = 9,
    mem_vsib64y = 10,
    mem_vsib32z = 11,
    mem_vsib64z = 12,
    r8_or_mem = 13,
    r16_or_mem = 14,
    r32_or_mem = 15,
    r32_or_mem_mpx = 16,
    r64_or_mem = 17,
    r64_or_mem_mpx = 18,
    mm_or_mem = 19,
    xmm_or_mem = 20,
    ymm_or_mem = 21,
    zmm_or_mem = 22,
    bnd_or_mem_mpx = 23,
    k_or_mem = 24,
    r8_reg = 25,
    r8_opcode = 26,
    r16_reg = 27,
    r16_reg_mem = 28,
    r16_rm = 29,
    r16_opcode = 30,
    r32_reg = 31,
    r32_reg_mem = 32,
    r32_rm = 33,
    r32_opcode = 34,
    r32_vvvv = 35,
    r64_reg = 36,
    r64_reg_mem = 37,
    r64_rm = 38,
    r64_opcode = 39,
    r64_vvvv = 40,
    seg_reg = 41,
    k_reg = 42,
    kp1_reg = 43,
    k_rm = 44,
    k_vvvv = 45,
    mm_reg = 46,
    mm_rm = 47,
    xmm_reg = 48,
    xmm_rm = 49,
    xmm_vvvv = 50,
    xmmp3_vvvv = 51,
    xmm_is4 = 52,
    xmm_is5 = 53,
    ymm_reg = 54,
    ymm_rm = 55,
    ymm_vvvv = 56,
    ymm_is4 = 57,
    ymm_is5 = 58,
    zmm_reg = 59,
    zmm_rm = 60,
    zmm_vvvv = 61,
    zmmp3_vvvv = 62,
    cr_reg = 63,
    dr_reg = 64,
    tr_reg = 65,
    bnd_reg = 66,
    es = 67,
    cs = 68,
    ss = 69,
    ds = 70,
    fs = 71,
    gs = 72,
    al = 73,
    cl = 74,
    ax = 75,
    dx = 76,
    eax = 77,
    rax = 78,
    st0 = 79,
    sti_opcode = 80,
    imm4_m2z = 81,
    imm8 = 82,
    imm8_const_1 = 83,
    imm8sex16 = 84,
    imm8sex32 = 85,
    imm8sex64 = 86,
    imm16 = 87,
    imm32 = 88,
    imm32sex64 = 89,
    imm64 = 90,
    seg_rSI = 91,
    es_rDI = 92,
    seg_rDI = 93,
    seg_rBX_al = 94,
    br16_1 = 95,
    br32_1 = 96,
    br64_1 = 97,
    br16_2 = 98,
    br32_4 = 99,
    br64_4 = 100,
    xbegin_2 = 101,
    xbegin_4 = 102,
    brdisp_2 = 103,
    brdisp_4 = 104,
    sibmem = 105,
    tmm_reg = 106,
    tmm_rm = 107,
    tmm_vvvv = 108,
}

Operand kind

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

None = 0

No operand

farbr2_2 = 1

Far branch 16-bit offset, 16-bit segment/selector

farbr4_2 = 2

Far branch 32-bit offset, 16-bit segment/selector

mem_offs = 3

Memory offset without a modrm byte (eg. MOV AL,[offset])

mem = 4

Memory (modrm)

mem_mpx = 5

Memory (modrm), MPX:

16/32-bit mode: must be 32-bit addressing

64-bit mode: 64-bit addressing is forced and must not be RIP relative

mem_mib = 6

Memory (modrm), MPX:

16/32-bit mode: must be 32-bit addressing

64-bit mode: 64-bit addressing is forced and must not be RIP relative

mem_vsib32x = 7

Memory (modrm), vsib32, XMM registers

mem_vsib64x = 8

Memory (modrm), vsib64, XMM registers

mem_vsib32y = 9

Memory (modrm), vsib32, YMM registers

mem_vsib64y = 10

Memory (modrm), vsib64, YMM registers

mem_vsib32z = 11

Memory (modrm), vsib32, ZMM registers

mem_vsib64z = 12

Memory (modrm), vsib64, ZMM registers

r8_or_mem = 13

8-bit GPR or memory

r16_or_mem = 14

16-bit GPR or memory

r32_or_mem = 15

32-bit GPR or memory

r32_or_mem_mpx = 16

32-bit GPR or memory, MPX: 16/32-bit mode: must be 32-bit addressing, 64-bit mode: 64-bit addressing is forced

r64_or_mem = 17

64-bit GPR or memory

r64_or_mem_mpx = 18

64-bit GPR or memory, MPX: 16/32-bit mode: must be 32-bit addressing, 64-bit mode: 64-bit addressing is forced

mm_or_mem = 19

MM register or memory

xmm_or_mem = 20

XMM register or memory

ymm_or_mem = 21

YMM register or memory

zmm_or_mem = 22

ZMM register or memory

bnd_or_mem_mpx = 23

BND register or memory, MPX: 16/32-bit mode: must be 32-bit addressing, 64-bit mode: 64-bit addressing is forced

k_or_mem = 24

K register or memory

r8_reg = 25

8-bit GPR encoded in the reg field of the modrm byte

r8_opcode = 26

8-bit GPR encoded in the low 3 bits of the opcode

r16_reg = 27

16-bit GPR encoded in the reg field of the modrm byte

r16_reg_mem = 28

16-bit GPR encoded in the reg field of the modrm byte. This is a memory operand and it uses the address size prefix (67h) not the operand size prefix (66h).

r16_rm = 29

16-bit GPR encoded in the mod + r/m fields of the modrm byte

r16_opcode = 30

16-bit GPR encoded in the low 3 bits of the opcode

r32_reg = 31

32-bit GPR encoded in the reg field of the modrm byte

r32_reg_mem = 32

32-bit GPR encoded in the reg field of the modrm byte. This is a memory operand and it uses the address size prefix (67h) not the operand size prefix (66h).

r32_rm = 33

32-bit GPR encoded in the mod + r/m fields of the modrm byte

r32_opcode = 34

32-bit GPR encoded in the low 3 bits of the opcode

r32_vvvv = 35

32-bit GPR encoded in the the V'vvvv field (VEX/EVEX/XOP)

r64_reg = 36

64-bit GPR encoded in the reg field of the modrm byte

r64_reg_mem = 37

64-bit GPR encoded in the reg field of the modrm byte. This is a memory operand and it uses the address size prefix (67h) not the operand size prefix (66h).

r64_rm = 38

64-bit GPR encoded in the mod + r/m fields of the modrm byte

r64_opcode = 39

64-bit GPR encoded in the low 3 bits of the opcode

r64_vvvv = 40

64-bit GPR encoded in the the V'vvvv field (VEX/EVEX/XOP)

seg_reg = 41

Segment register encoded in the reg field of the modrm byte

k_reg = 42

K register encoded in the reg field of the modrm byte

kp1_reg = 43

K register (+1) encoded in the reg field of the modrm byte

k_rm = 44

K register encoded in the mod + r/m fields of the modrm byte

k_vvvv = 45

K register encoded in the the V'vvvv field (VEX/EVEX/MVEX/XOP)

mm_reg = 46

MM register encoded in the reg field of the modrm byte

mm_rm = 47

MM register encoded in the mod + r/m fields of the modrm byte

xmm_reg = 48

XMM register encoded in the reg field of the modrm byte

xmm_rm = 49

XMM register encoded in the mod + r/m fields of the modrm byte

xmm_vvvv = 50

XMM register encoded in the the V'vvvv field (VEX/EVEX/XOP)

xmmp3_vvvv = 51

XMM register (+3) encoded in the the V'vvvv field (VEX/EVEX/XOP)

xmm_is4 = 52

XMM register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only XMM0-XMM15)

xmm_is5 = 53

XMM register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only XMM0-XMM15)

ymm_reg = 54

YMM register encoded in the reg field of the modrm byte

ymm_rm = 55

YMM register encoded in the mod + r/m fields of the modrm byte

ymm_vvvv = 56

YMM register encoded in the the V'vvvv field (VEX/EVEX/XOP)

ymm_is4 = 57

YMM register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only YMM0-YMM15)

ymm_is5 = 58

YMM register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only YMM0-YMM15)

zmm_reg = 59

ZMM register encoded in the reg field of the modrm byte

zmm_rm = 60

ZMM register encoded in the mod + r/m fields of the modrm byte

zmm_vvvv = 61

ZMM register encoded in the the V'vvvv field (VEX/EVEX/MVEX/XOP)

zmmp3_vvvv = 62

ZMM register (+3) encoded in the the V'vvvv field (VEX/EVEX/XOP)

cr_reg = 63

CR register encoded in the reg field of the modrm byte

dr_reg = 64

DR register encoded in the reg field of the modrm byte

tr_reg = 65

TR register encoded in the reg field of the modrm byte

bnd_reg = 66

BND register encoded in the reg field of the modrm byte

es = 67

ES register

cs = 68

CS register

ss = 69

SS register

ds = 70

DS register

fs = 71

FS register

gs = 72

GS register

al = 73

AL register

cl = 74

CL register

ax = 75

AX register

dx = 76

DX register

eax = 77

EAX register

rax = 78

RAX register

st0 = 79

ST(0) register

sti_opcode = 80

ST(i) register encoded in the low 3 bits of the opcode

imm4_m2z = 81

4-bit immediate (m2z field, low 4 bits of the /is5 immediate, eg. VPERMIL2PS)

imm8 = 82

8-bit immediate

imm8_const_1 = 83

Constant 1 (8-bit immediate)

imm8sex16 = 84

8-bit immediate sign extended to 16 bits

imm8sex32 = 85

8-bit immediate sign extended to 32 bits

imm8sex64 = 86

8-bit immediate sign extended to 64 bits

imm16 = 87

16-bit immediate

imm32 = 88

32-bit immediate

imm32sex64 = 89

32-bit immediate sign extended to 64 bits

imm64 = 90

64-bit immediate

seg_rSI = 91

seg:[rSI] memory operand (string instructions)

es_rDI = 92

es:[rDI] memory operand (string instructions)

seg_rDI = 93

seg:[rDI] memory operand ((V)MASKMOVQ instructions)

seg_rBX_al = 94

seg:[rBX+al] memory operand (XLATB instruction)

br16_1 = 95

16-bit branch, 1-byte signed relative offset

br32_1 = 96

32-bit branch, 1-byte signed relative offset

br64_1 = 97

64-bit branch, 1-byte signed relative offset

br16_2 = 98

16-bit branch, 2-byte signed relative offset

br32_4 = 99

32-bit branch, 4-byte signed relative offset

br64_4 = 100

64-bit branch, 4-byte signed relative offset

xbegin_2 = 101

XBEGIN, 2-byte signed relative offset

xbegin_4 = 102

XBEGIN, 4-byte signed relative offset

brdisp_2 = 103

2-byte branch offset (JMPE instruction)

brdisp_4 = 104

4-byte branch offset (JMPE instruction)

sibmem = 105

Memory (modrm) and the sib byte must be present

tmm_reg = 106

TMM register encoded in the reg field of the modrm byte

tmm_rm = 107

TMM register encoded in the mod + r/m fields of the modrm byte

tmm_vvvv = 108

TMM register encoded in the the V'vvvv field (VEX/EVEX/XOP)

Implementations

impl OpCodeOperandKind

pub fn values( ) -> impl Iterator<Item = OpCodeOperandKind> + DoubleEndedIterator + ExactSizeIterator + FusedIterator

Iterates over all OpCodeOperandKind enum values

Trait Implementations

impl Clone for OpCodeOperandKind

fn clone(&self) -> OpCodeOperandKind

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for OpCodeOperandKind

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for OpCodeOperandKind

fn default() -> Self

Returns the “default value” for a type.

impl<'de> Deserialize<'de> for OpCodeOperandKind

fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>

where D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl Hash for OpCodeOperandKind

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl Ord for OpCodeOperandKind

fn cmp(&self, other: &OpCodeOperandKind) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

where Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

where Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

where Self: Sized + PartialOrd,

Restrict a value to a certain interval.

impl PartialEq for OpCodeOperandKind

fn eq(&self, other: &OpCodeOperandKind) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl PartialOrd for OpCodeOperandKind

fn partial_cmp(&self, other: &OpCodeOperandKind) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

This method tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

This method tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

This method tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

This method tests greater than or equal to (for self and other) and is used by the >= operator.

impl Serialize for OpCodeOperandKind

fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>

where S: Serializer,

Serialize this value into the given Serde serializer.

impl TryFrom<usize> for OpCodeOperandKind

type Error = IcedError

The type returned in the event of a conversion error.

fn try_from(value: usize) -> Result<Self, Self::Error>

Performs the conversion.

impl Copy for OpCodeOperandKind

impl Eq for OpCodeOperandKind

impl StructuralEq for OpCodeOperandKind

impl StructuralPartialEq for OpCodeOperandKind