Struct iced_x86::DecoderOptions

pub struct DecoderOptions;

Decoder options

Implementations

impl DecoderOptions

pub const NONE: u32

No option is enabled

pub const NO_INVALID_CHECK: u32

Disable some checks for invalid encodings of instructions, eg. most instructions can’t use a LOCK prefix so if one is found, they’re decoded as Code::INVALID unless this option is enabled.

pub const AMD: u32

AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS, UD0 has no modr/m byte, decode LOCK MOV CR. The AMD decoder can still decode Intel instructions.

pub const FORCE_RESERVED_NOP: u32

Decode opcodes 0F0D and 0F18-0F1F as reserved-nop instructions (eg. Code::Reservednop_rm32_r32_0F1D)

pub const UMOV: u32

Decode UMOV instructions

pub const XBTS: u32

Decode XBTS/IBTS

pub const CMPXCHG486A: u32

Decode 0FA6/0FA7 as CMPXCHG

pub const OLD_FPU: u32

Decode some old removed FPU instructions (eg. FRSTPM)

pub const PCOMMIT: u32

Decode PCOMMIT

pub const LOADALL286: u32

Decode 286 STOREALL/LOADALL (0F04 and 0F05)

pub const LOADALL386: u32

Decode 386 LOADALL

pub const CL1INVMB: u32

Decode CL1INVMB

pub const MOV_TR: u32

Decode MOV r32,tr and MOV tr,r32

pub const JMPE: u32

Decode JMPE instructions

pub const NO_PAUSE: u32

Don’t decode PAUSE, decode NOP instead

pub const NO_WBNOINVD: u32

Don’t decode WBNOINVD, decode WBINVD instead

pub const UDBG: u32

Decode undocumented Intel RDUDBG and WRUDBG instructions

pub const NO_MPFX_0FBC: u32

Don’t decode TZCNT, decode BSF instead

pub const NO_MPFX_0FBD: u32

Don’t decode LZCNT, decode BSR instead

pub const NO_LAHF_SAHF_64: u32

Don’t decode LAHF and SAHF in 64-bit mode

pub const MPX: u32

Decode MPX instructions

pub const CYRIX: u32

Decode most Cyrix instructions: FPU, EMMI, SMM, DDI

pub const CYRIX_SMINT_0F7E: u32

Decode Cyrix SMINT 0F7E (Cyrix 6x86 or earlier)

pub const CYRIX_DMI: u32

Decode Cyrix DMI instructions (AMD Geode GX/LX)

pub const ALTINST: u32

Decode Centaur ALTINST