Enum iced_x86::OpCodeOperandKind [−][src]
#[non_exhaustive] pub enum OpCodeOperandKind {}Show variants
None, farbr2_2, farbr4_2, mem_offs, mem, mem_mpx, mem_mib, mem_vsib32x, mem_vsib64x, mem_vsib32y, mem_vsib64y, mem_vsib32z, mem_vsib64z, r8_or_mem, r16_or_mem, r32_or_mem, r32_or_mem_mpx, r64_or_mem, r64_or_mem_mpx, mm_or_mem, xmm_or_mem, ymm_or_mem, zmm_or_mem, bnd_or_mem_mpx, k_or_mem, r8_reg, r8_opcode, r16_reg, r16_reg_mem, r16_rm, r16_opcode, r32_reg, r32_reg_mem, r32_rm, r32_opcode, r32_vvvv, r64_reg, r64_reg_mem, r64_rm, r64_opcode, r64_vvvv, seg_reg, k_reg, kp1_reg, k_rm, k_vvvv, mm_reg, mm_rm, xmm_reg, xmm_rm, xmm_vvvv, xmmp3_vvvv, xmm_is4, xmm_is5, ymm_reg, ymm_rm, ymm_vvvv, ymm_is4, ymm_is5, zmm_reg, zmm_rm, zmm_vvvv, zmmp3_vvvv, cr_reg, dr_reg, tr_reg, bnd_reg, es, cs, ss, ds, fs, gs, al, cl, ax, dx, eax, rax, st0, sti_opcode, imm4_m2z, imm8, imm8_const_1, imm8sex16, imm8sex32, imm8sex64, imm16, imm32, imm32sex64, imm64, seg_rSI, es_rDI, seg_rDI, seg_rBX_al, br16_1, br32_1, br64_1, br16_2, br32_4, br64_4, xbegin_2, xbegin_4, brdisp_2, brdisp_4, sibmem, tmm_reg, tmm_rm, tmm_vvvv,
Expand description
Operand kind
Variants (Non-exhaustive)
This enum is marked as non-exhaustive
No operand
Far branch 16-bit offset, 16-bit segment/selector
Far branch 32-bit offset, 16-bit segment/selector
Memory offset without a modrm byte (eg. MOV AL,[offset]
)
Memory (modrm)
Memory (modrm), MPX:
16/32-bit mode: must be 32-bit addressing
64-bit mode: 64-bit addressing is forced and must not be RIP relative
Memory (modrm), MPX:
16/32-bit mode: must be 32-bit addressing
64-bit mode: 64-bit addressing is forced and must not be RIP relative
Memory (modrm), vsib32, XMM
registers
Memory (modrm), vsib64, XMM
registers
Memory (modrm), vsib32, YMM
registers
Memory (modrm), vsib64, YMM
registers
Memory (modrm), vsib32, ZMM
registers
Memory (modrm), vsib64, ZMM
registers
8-bit GPR or memory
16-bit GPR or memory
32-bit GPR or memory
32-bit GPR or memory, MPX: 16/32-bit mode: must be 32-bit addressing, 64-bit mode: 64-bit addressing is forced
64-bit GPR or memory
64-bit GPR or memory, MPX: 16/32-bit mode: must be 32-bit addressing, 64-bit mode: 64-bit addressing is forced
MM
register or memory
XMM
register or memory
YMM
register or memory
ZMM
register or memory
BND
register or memory, MPX: 16/32-bit mode: must be 32-bit addressing, 64-bit mode: 64-bit addressing is forced
K
register or memory
8-bit GPR encoded in the reg
field of the modrm byte
8-bit GPR encoded in the low 3 bits of the opcode
16-bit GPR encoded in the reg
field of the modrm byte
16-bit GPR encoded in the reg
field of the modrm byte. This is a memory operand and it uses the address size prefix (67h
) not the operand size prefix (66h
).
16-bit GPR encoded in the mod + r/m
fields of the modrm byte
16-bit GPR encoded in the low 3 bits of the opcode
32-bit GPR encoded in the reg
field of the modrm byte
32-bit GPR encoded in the reg
field of the modrm byte. This is a memory operand and it uses the address size prefix (67h
) not the operand size prefix (66h
).
32-bit GPR encoded in the mod + r/m
fields of the modrm byte
32-bit GPR encoded in the low 3 bits of the opcode
32-bit GPR encoded in the the V'vvvv
field (VEX/EVEX/XOP)
64-bit GPR encoded in the reg
field of the modrm byte
64-bit GPR encoded in the reg
field of the modrm byte. This is a memory operand and it uses the address size prefix (67h
) not the operand size prefix (66h
).
64-bit GPR encoded in the mod + r/m
fields of the modrm byte
64-bit GPR encoded in the low 3 bits of the opcode
64-bit GPR encoded in the the V'vvvv
field (VEX/EVEX/XOP)
Segment register encoded in the reg
field of the modrm byte
K
register encoded in the reg
field of the modrm byte
K
register (+1) encoded in the reg
field of the modrm byte
K
register encoded in the mod + r/m
fields of the modrm byte
K
register encoded in the the V'vvvv
field (VEX/EVEX/XOP)
MM
register encoded in the reg
field of the modrm byte
MM
register encoded in the mod + r/m
fields of the modrm byte
XMM
register encoded in the reg
field of the modrm byte
XMM
register encoded in the mod + r/m
fields of the modrm byte
XMM
register encoded in the the V'vvvv
field (VEX/EVEX/XOP)
XMM
register (+3) encoded in the the V'vvvv
field (VEX/EVEX/XOP)
XMM
register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only XMM0
-XMM15
)
XMM
register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only XMM0
-XMM15
)
YMM
register encoded in the reg
field of the modrm byte
YMM
register encoded in the mod + r/m
fields of the modrm byte
YMM
register encoded in the the V'vvvv
field (VEX/EVEX/XOP)
YMM
register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only YMM0
-YMM15
)
YMM
register encoded in the the high 4 bits of the last 8-bit immediate (VEX/XOP only so only YMM0
-YMM15
)
ZMM
register encoded in the reg
field of the modrm byte
ZMM
register encoded in the mod + r/m
fields of the modrm byte
ZMM
register encoded in the the V'vvvv
field (VEX/EVEX/XOP)
ZMM
register (+3) encoded in the the V'vvvv
field (VEX/EVEX/XOP)
CR
register encoded in the reg
field of the modrm byte
DR
register encoded in the reg
field of the modrm byte
TR
register encoded in the reg
field of the modrm byte
BND
register encoded in the reg
field of the modrm byte
ES
register
CS
register
SS
register
DS
register
FS
register
GS
register
AL
register
CL
register
AX
register
DX
register
EAX
register
RAX
register
ST(0)
register
ST(i)
register encoded in the low 3 bits of the opcode
4-bit immediate (m2z field, low 4 bits of the /is5 immediate, eg. VPERMIL2PS
)
8-bit immediate
Constant 1 (8-bit immediate)
8-bit immediate sign extended to 16 bits
8-bit immediate sign extended to 32 bits
8-bit immediate sign extended to 64 bits
16-bit immediate
32-bit immediate
32-bit immediate sign extended to 64 bits
64-bit immediate
seg:[rSI]
memory operand (string instructions)
es:[rDI]
memory operand (string instructions)
seg:[rDI]
memory operand ((V)MASKMOVQ
instructions)
seg:[rBX+al]
memory operand (XLATB
instruction)
16-bit branch, 1-byte signed relative offset
32-bit branch, 1-byte signed relative offset
64-bit branch, 1-byte signed relative offset
16-bit branch, 2-byte signed relative offset
32-bit branch, 4-byte signed relative offset
64-bit branch, 4-byte signed relative offset
XBEGIN
, 2-byte signed relative offset
XBEGIN
, 4-byte signed relative offset
2-byte branch offset (JMPE
instruction)
4-byte branch offset (JMPE
instruction)
Memory (modrm) and the sib byte must be present
TMM
register encoded in the reg
field of the modrm byte
TMM
register encoded in the mod + r/m
fields of the modrm byte
TMM
register encoded in the the V'vvvv
field (VEX/EVEX/XOP)
Implementations
pub fn values(
) -> impl Iterator<Item = OpCodeOperandKind> + DoubleEndedIterator + ExactSizeIterator + FusedIterator
[src]
pub fn values(
) -> impl Iterator<Item = OpCodeOperandKind> + DoubleEndedIterator + ExactSizeIterator + FusedIterator
[src]Iterates over all OpCodeOperandKind
enum values
Trait Implementations
This method returns an ordering between self
and other
values if one exists. Read more
This method tests less than (for self
and other
) and is used by the <
operator. Read more
This method tests less than or equal to (for self
and other
) and is used by the <=
operator. Read more
This method tests greater than (for self
and other
) and is used by the >
operator. Read more
Auto Trait Implementations
impl RefUnwindSafe for OpCodeOperandKind
impl Send for OpCodeOperandKind
impl Sync for OpCodeOperandKind
impl Unpin for OpCodeOperandKind
impl UnwindSafe for OpCodeOperandKind
Blanket Implementations
Mutably borrows from an owned value. Read more