Enum iced_x86::CpuidFeature [−][src]
CPUID
feature flags
Variants (Non-exhaustive)
8086 or later
8086 only
80186 or later
80286 or later
80286 only
80386 or later
80386 only
80386 A0-B0 stepping only (XBTS
, IBTS
instructions)
Intel486 or later
Intel486 A stepping only (CMPXCHG
)
UMOV (80386 and Intel486)
IA-64
CPUID.80000001H:EDX.LM[bit 29]
CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19]
CPUID.01H:ECX.AES[bit 25]
CPUID.01H:ECX.AVX[bit 28]
CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]
CPUID.(EAX=07H, ECX=0H):EDX.AVX512_4FMAPS[bit 3]
CPUID.(EAX=07H, ECX=0H):EDX.AVX512_4VNNIW[bit 2]
CPUID.(EAX=07H, ECX=1H):EAX.AVX512_BF16[bit 5]
CPUID.(EAX=07H, ECX=0H):ECX.AVX512_BITALG[bit 12]
CPUID.(EAX=07H, ECX=0H):EBX.AVX512_IFMA[bit 21]
CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VBMI[bit 1]
CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VBMI2[bit 6]
CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VNNI[bit 11]
CPUID.(EAX=07H, ECX=0H):EDX.AVX512_VP2INTERSECT[bit 08]
CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VPOPCNTDQ[bit 14]
CPUID.(EAX=07H, ECX=0H):EBX.AVX512BW[bit 30]
CPUID.(EAX=07H, ECX=0H):EBX.AVX512CD[bit 28]
CPUID.(EAX=07H, ECX=0H):EBX.AVX512DQ[bit 17]
CPUID.(EAX=07H, ECX=0H):EBX.AVX512ER[bit 27]
CPUID.(EAX=07H, ECX=0H):EBX.AVX512F[bit 16]
CPUID.(EAX=07H, ECX=0H):EBX.AVX512PF[bit 26]
CPUID.(EAX=07H, ECX=0H):EBX.AVX512VL[bit 31]
CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]
CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]
CPUID.(EAX=07H, ECX=0H):EDX.CET_IBT[bit 20]
CPUID.(EAX=07H, ECX=0H):ECX.CET_SS[bit 7]
CL1INVMB
instruction (Intel SCC = Single-Chip Computer)
CPUID.(EAX=07H, ECX=0H):ECX.CLDEMOTE[bit 25]
CPUID.(EAX=07H, ECX=0H):EBX.CLFLUSHOPT[bit 23]
CPUID.01H:EDX.CLFSH[bit 19]
CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24]
CPUID.80000008H:EBX.CLZERO[bit 0]
CPUID.01H:EDX.CMOV[bit 15]
CPUID.01H:ECX.CMPXCHG16B[bit 13]
RFLAGS.ID
can be toggled
CPUID.01H:EDX.CX8[bit 8]
CPUID.80000001H:EDX.3DNOW[bit 31]
CPUID.80000001H:EDX.3DNOWEXT[bit 30]
CPUID.(EAX=12H, ECX=0H):EAX.OSS[bit 5]
CPUID.(EAX=07H, ECX=0H):ECX.ENQCMD[bit 29]
CPUID.01H:ECX.F16C[bit 29]
CPUID.01H:ECX.FMA[bit 12]
CPUID.80000001H:ECX.FMA4[bit 16]
8087 or later (CPUID.01H:EDX.FPU[bit 0])
80287 or later
80287XL only
80387 or later
80387SL only
CPUID.(EAX=07H, ECX=0H):EBX.FSGSBASE[bit 0]
CPUID.01H:EDX.FXSR[bit 24]
Cyrix (AMD Geode GX/LX) 3DNow! instructions
CPUID.(EAX=07H, ECX=0H):ECX.GFNI[bit 8]
CPUID.(EAX=07H, ECX=0H):EBX.HLE[bit 4]
IA32_VMX_EPT_VPID_CAP[bit 20]
CPUID.(EAX=07H, ECX=0H):EBX.INVPCID[bit 10]
IA32_VMX_EPT_VPID_CAP[bit 32]
CPUID.80000001H:ECX.LWP[bit 15]
CPUID.80000001H:ECX.LZCNT[bit 5]
CPUID.80000008H:EBX.MCOMMIT[bit 8]
CPUID.01H:EDX.MMX[bit 23]
CPUID.01H:ECX.MONITOR[bit 3]
CPUID.80000001H:ECX.MONITORX[bit 29]
CPUID.01H:ECX.MOVBE[bit 22]
CPUID.(EAX=07H, ECX=0H):ECX.MOVDIR64B[bit 28]
CPUID.(EAX=07H, ECX=0H):ECX.MOVDIRI[bit 27]
CPUID.(EAX=07H, ECX=0H):EBX.MPX[bit 14]
CPUID.01H:EDX.MSR[bit 5]
Multi-byte nops (0F1F /0
): CPUID.01H.EAX[Bits 11:8] = 0110B or 1111B
CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.ACE[Bits 7:6] = 11B ([6] = exists, [7] = enabled)
CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.PHE[Bits 11:10] = 11B ([10] = exists, [11] = enabled)
CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.PMM[Bits 13:12] = 11B ([12] = exists, [13] = enabled)
CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.RNG[Bits 3:2] = 11B ([2] = exists, [3] = enabled)
PAUSE
instruction (Pentium 4 or later)
CPUID.01H:ECX.PCLMULQDQ[bit 1]
CPUID.(EAX=07H, ECX=0H):EBX.PCOMMIT[bit 22]
CPUID.(EAX=07H, ECX=0H):EDX.PCONFIG[bit 18]
CPUID.(EAX=07H, ECX=0H):ECX.PKU[bit 3]
CPUID.01H:ECX.POPCNT[bit 23]
CPUID.80000001H:ECX.PREFETCHW[bit 8]
CPUID.(EAX=07H, ECX=0H):ECX.PREFETCHWT1[bit 0]
CPUID.(EAX=14H, ECX=0H):EBX.PTWRITE[bit 4]
CPUID.(EAX=07H, ECX=0H):ECX.RDPID[bit 22]
RDPMC
instruction (Pentium MMX or later, or Pentium Pro or later)
CPUID.80000008H:EBX.RDPRU[bit 4]
CPUID.01H:ECX.RDRAND[bit 30]
CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18]
CPUID.80000001H:EDX.RDTSCP[bit 27]
CPUID.(EAX=07H, ECX=0H):EBX.RTM[bit 11]
CPUID.01H:EDX.SEP[bit 11]
CPUID.(EAX=12H, ECX=0H):EAX.SGX1[bit 0]
CPUID.(EAX=07H, ECX=0H):EBX.SHA[bit 29]
CPUID.80000001H:ECX.SKINIT[bit 12]
CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20]
CPUID.01H:ECX.SMX[bit 6]
CPUID.01H:EDX.SSE[bit 25]
CPUID.01H:EDX.SSE2[bit 26]
CPUID.01H:ECX.SSE3[bit 0]
CPUID.01H:ECX.SSE4_1[bit 19]
CPUID.01H:ECX.SSE4_2[bit 20]
CPUID.80000001H:ECX.SSE4A[bit 6]
CPUID.01H:ECX.SSSE3[bit 9]
CPUID.80000001H:ECX.SVM[bit 2]
CPUID.8000001FH:EAX.SEV-ES[bit 3]
CPUID.80000001H:EDX.SYSCALL[bit 11]
CPUID.80000001H:ECX.TBM[bit 21]
CPUID.01H:EDX.TSC[bit 4]
CPUID.(EAX=07H, ECX=0H):ECX.VAES[bit 9]
CPUID.01H:ECX.VMX[bit 5]
CPUID.(EAX=07H, ECX=0H):ECX.VPCLMULQDQ[bit 10]
CPUID.(EAX=07H, ECX=0H):ECX.WAITPKG[bit 5]
CPUID.(EAX=80000008H, ECX=0H):EBX.WBNOINVD[bit 9]
CPUID.80000001H:ECX.XOP[bit 11]
CPUID.01H:ECX.XSAVE[bit 26]
CPUID.(EAX=0DH, ECX=1H):EAX.XSAVEC[bit 1]
CPUID.(EAX=0DH, ECX=1H):EAX.XSAVEOPT[bit 0]
CPUID.(EAX=0DH, ECX=1H):EAX.XSAVES[bit 3]
CPUID.8000001FH:EAX.SEV-SNP[bit 4]
CPUID.(EAX=07H, ECX=0H):EDX.SERIALIZE[bit 14]
CPUID.(EAX=07H, ECX=0H):EDX.TSXLDTRK[bit 16]
CPUID.80000008H:EBX.INVLPGB[bit 3]
CPUID.(EAX=07H, ECX=0H):EDX.AMX-BF16[bit 22]
CPUID.(EAX=07H, ECX=0H):EDX.AMX-TILE[bit 24]
CPUID.(EAX=07H, ECX=0H):EDX.AMX-INT8[bit 25]
Cyrix FPU instructions (Cyrix, AMD Geode GX/LX)
Cyrix SMM instructions: SVDC
, RSDC
, SVLDT
, RSLDT
, SVTS
, RSTS
(Cyrix, AMD Geode GX/LX)
Cyrix SMINT 0F38
(6x86MX and later, AMD Geode GX/LX)
Cyrix SMINT 0F7E
(6x86 or earlier)
Cyrix SMM instructions: RDSHR
, WRSHR
(6x86MX, M II, Cyrix III)
Cyrix DDI instructions: BB0_Reset
, BB1_Reset
, CPU_READ
, CPU_WRITE
(MediaGX, GXm, GXLV, GX1)
Cyrix AND CPUID.80000001H:EDX.EMMI[bit 24]
Cyrix DMI instructions: DMINT
, RDM
(AMD Geode GX/LX)
CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.AIS[Bits 1:0] = 11B ([0] = exists, [1] = enabled)
MOV to/from TR (80386, Intel486, Cyrix, Geode)
RSM
instruction (some 386s, some 486s, Pentium and later)
CPUID.(EAX=??H, ECX=?H):???.????[bit ??]
CPUID.(EAX=07H, ECX=0H):ECX.KL[bit 23]
CPUID.19H:EBX.AESKLE[bit 0]
CPUID.19H:EBX.WIDE_KL[bit 2]
CPUID.(EAX=07H, ECX=0H):EDX.UINTR[bit 5]
CPUID.(EAX=07H, ECX=01H):EAX.HRESET[bit 22]
CPUID.(EAX=07H, ECX=01H):EAX.AVX-VNNI[bit 4]
CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.GMI[Bits 5:4] = 11B ([4] = exists, [5] = enabled)
Trait Implementations
impl Clone for CpuidFeature
[src]
fn clone(&self) -> CpuidFeature
[src]
pub fn clone_from(&mut self, source: &Self)
1.0.0[src]
impl Copy for CpuidFeature
[src]
impl Debug for CpuidFeature
[src]
impl Default for CpuidFeature
[src]
impl Eq for CpuidFeature
[src]
impl Hash for CpuidFeature
[src]
fn hash<__H: Hasher>(&self, state: &mut __H)
[src]
pub fn hash_slice<H>(data: &[Self], state: &mut H) where
H: Hasher,
1.3.0[src]
H: Hasher,
impl Ord for CpuidFeature
[src]
fn cmp(&self, other: &CpuidFeature) -> Ordering
[src]
#[must_use]pub fn max(self, other: Self) -> Self
1.21.0[src]
#[must_use]pub fn min(self, other: Self) -> Self
1.21.0[src]
#[must_use]pub fn clamp(self, min: Self, max: Self) -> Self
1.50.0[src]
impl PartialEq<CpuidFeature> for CpuidFeature
[src]
fn eq(&self, other: &CpuidFeature) -> bool
[src]
#[must_use]pub fn ne(&self, other: &Rhs) -> bool
1.0.0[src]
impl PartialOrd<CpuidFeature> for CpuidFeature
[src]
fn partial_cmp(&self, other: &CpuidFeature) -> Option<Ordering>
[src]
#[must_use]pub fn lt(&self, other: &Rhs) -> bool
1.0.0[src]
#[must_use]pub fn le(&self, other: &Rhs) -> bool
1.0.0[src]
#[must_use]pub fn gt(&self, other: &Rhs) -> bool
1.0.0[src]
#[must_use]pub fn ge(&self, other: &Rhs) -> bool
1.0.0[src]
impl StructuralEq for CpuidFeature
[src]
impl StructuralPartialEq for CpuidFeature
[src]
Auto Trait Implementations
impl RefUnwindSafe for CpuidFeature
[src]
impl Send for CpuidFeature
[src]
impl Sync for CpuidFeature
[src]
impl Unpin for CpuidFeature
[src]
impl UnwindSafe for CpuidFeature
[src]
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
[src]
T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
[src]
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
[src]
T: ?Sized,
pub fn borrow_mut(&mut self) -> &mut T
[src]
impl<T> From<T> for T
[src]
impl<T, U> Into<U> for T where
U: From<T>,
[src]
U: From<T>,
impl<T> ToOwned for T where
T: Clone,
[src]
T: Clone,
type Owned = T
The resulting type after obtaining ownership.
pub fn to_owned(&self) -> T
[src]
pub fn clone_into(&self, target: &mut T)
[src]
impl<T, U> TryFrom<U> for T where
U: Into<T>,
[src]
U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
pub fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
[src]
impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
[src]
U: TryFrom<T>,