hyperlight_common/arch/amd64/layout.rs
1// SPDX-License-Identifier: Apache-2.0
2// Copyright 2025 The Hyperlight Authors.
3
4// The addresses in this file should be coordinated with
5// src/hyperlight_guest/src/arch/amd64/layout.rs and
6// src/hyperlight_guest_bin/src/arch/amd64/layout.rs
7
8/// We have this the top of the page below the top of memory in order
9/// to make working with start/end ptrs in a few places more
10/// convenient (not needing to worry about overflow)
11pub const SCRATCH_TOP_GVA: usize = 0xffff_ffff_ffff_efff;
12pub const SNAPSHOT_PT_GVA_MIN: usize = 0xffff_8000_0000_0000;
13pub const SNAPSHOT_PT_GVA_MAX: usize = 0xffff_80ff_ffff_ffff;
14
15/// We assume 36-bit IPAs for now, since every amd64 processor
16/// supports at least 36 bits. Almost all of them support at least 40
17/// bits, so we could consider bumping this in the future if we were
18/// ever memory-constrained.
19pub const SCRATCH_TOP_GPA: usize = 0x0000_000f_ffff_ffff;
20
21pub fn io_page() -> Option<(u64, u64)> {
22 None
23}
24
25/// On amd64, this is:
26/// - Two pages for the TSS and IDT
27/// - (up to) 4 pages for the PTEs for mapping that (including CoW'ing the root PT)
28/// - A page for the smallest possible non-exception stack
29/// - (up to) 3 pages for mapping that
30/// - Two pages for the exception stack and metadata
31/// - A page-aligned amount of memory for I/O buffers (for now)
32pub fn min_scratch_size(input_data_size: usize, output_data_size: usize) -> usize {
33 (input_data_size + output_data_size).next_multiple_of(crate::vmem::PAGE_SIZE)
34 + 12 * crate::vmem::PAGE_SIZE
35}