Crate hydroplane 

hydroplane: float-agnostic, ISPC-style SPMD/SIMD infrastructure.

Write one kernel generic over the scalar element (Scalar: f32, f64, f16, bf16); dispatch() runs it on the widest backend runtime CPU detection finds, else the portable ScalarBackend (also the rust-gpu/SPIR-V lowering target). Kernels never name a backend. Stable Rust, no_std-compatible, no SIMD-crate dependency; f16/bf16 come from the half crate, re-exported as f16/bf16.

Re-exports

pub use backend::Backend;

pub use backend::BackendAll;

pub use backend::ScalarBackend;

pub use dispatch::Kernel;

pub use dispatch::SimdDispatch;

pub use dispatch::dispatch;

pub use dispatch::run_scalar;

pub use dense::Diag;

pub use dense::Mat;

pub use dense::Side;

pub use dense::Trans;

pub use dense::Uplo;

pub use dense::col_sums;

pub use dense::fro_norm;

pub use dense::gemv;

pub use dense::row_sums;

pub use dense::MatMut;

pub use dense::gemm;

pub use dense::potrf;

pub use dense::syrk;

pub use dense::trsm;

pub use matrix::Accumulator;

pub use matrix::Layout;

pub use matrix::MatrixA;

pub use matrix::MatrixB;

pub use matrix::MatrixBackend;

pub use matrix::MatrixDispatch;

pub use matrix::MatrixKernel;

pub use matrix::Role;

pub use matrix::Tile;

pub use matrix::Tiles;

pub use matrix::dispatch_matrix;

pub use matrix::run_matrix_scalar;

pub use scalar::FloatScalar;

pub use scalar::IntScalar;

pub use scalar::Scalar;

pub use varying::ChunksExact;

pub use varying::Varying;

pub use varying::VaryingI32;

pub use varying::VaryingU32;

pub use varying::Mask;

pub use varying::Gang;

pub use cols::Cols;

pub use soa::Soa;

pub use num_traits;

Modules

arch

Low-level SIMD primitives (raw asm!) and the ARM backend-selection policy. Scalable (SVE/RVV) registers can’t live in Rust structs, so ops work on fixed-size memory images: one byte width = one vector length = one backend.

backend

ISA tokens: a Backend<T> is a zero-sized token identifying an instruction set (scalar, AVX2, NEON, …, GPU subgroup) for a specific scalar T, each (ISA, scalar) pair its own impl. The lane count is a fn, not a const: the GPU subgroup only learns it at runtime.

cols

Fixed-arity bundles of SoA columns: Cols owns N parallel Vec<T> planes and hands out [&[T]; N] / [&mut [T]; N] views. The planes are unpadded, so kernels over Cols views use the masked-tail combinators (or load_partial) rather than sentinel padding.

dense

Runtime-dimensioned dense linear algebra (the compile-time tile counterpart is matrix). Every routine goes to Apple Accelerate where present, otherwise to a fallback built on the SIMD backend (Gang/Varying).

dispatch

Entry points that pick a Backend and run a generic Kernel: runtime CPU detection chooses the widest implemented backend per scalar (build-time target_features on no-std or under --cfg hp_static_dispatch), with ScalarBackend as the universal fallback.

matrix

Portable tile matrix-multiply: MatrixBackend extends the element-wise Backend with a 2-D tile and the fused multiply-add D = A·B + C, lowered per backend. Mixed precision follows FloatScalar::Compute: an f16 matmul accumulates in f32.

scalar

The “uniform” scalar element abstraction: Scalar is the element a kernel operates on. Each float scalar declares FloatScalar::Compute, the precision its math is carried out in — the type itself for f32/f64; f32 for f16/bf16, which widen-compute-narrow.

soa

Columnar (SoA) storage padded to MAX_LANES so kernels never need a remainder path; tail lanes take a caller-chosen fill (e.g. NaN radius). Requires alloc.

varying

The ergonomic “varying” surface: Gang is the load/splat context, Varying/Mask wrap a whole backend register (the ISPC “varying”) with operator overloads, so kernels read like ordinary scalar Rust. Everything is Copy and monomorphizes per (Backend, Scalar).

Structs

bf16

f16/bf16 element types (from the half crate), usable anywhere a Scalar is expected. A 16-bit floating point type implementing the bfloat16 format.

f16

f16/bf16 element types (from the half crate), usable anywhere a Scalar is expected. A 16-bit floating point type implementing the IEEE 754-2008 standard binary16 a.k.a “half” format.

Constants

MAX_LANES

Padding granularity: the widest lane count we target (AVX-512-FP16 is 32-wide f16). Every backend’s lane count (1, 2, 4, 8, 16, 32) divides this, so a full-register loop never has a remainder, and a single inline [T; MAX_LANES] buffer holds any one register.

MAX_UNROLL

Upper bound on a backend’s UNROLL: the most independent accumulator chains any reduction unrolls to. Sizes the fixed [init; MAX_UNROLL] chain array, so a backend’s UNROLL must not exceed it.

Attribute Macros

kernel

The #[kernel] attribute: write a Kernel/MatrixKernel as a plain generic function. Contexts, tuning flags (tiny, noalias, unroll = N), the generated <name>_on companion for calling one kernel from another without re-dispatching, and the matrix form are all documented on the attribute itself. Generate a Kernel (or, with #[kernel(matrix)], a MatrixKernel) and a dispatching wrapper from one annotated function. See the crate docs for the full shape.