hydro2_network/
test_wire.rs

1// ---------------- [ File: src/test_wire.rs ]
2crate::ix!();
3
4#[derive(NetworkWire,Default,PartialEq,Eq,Debug,Clone)]
5#[available_operators(
6    op="AddOp",
7    op="ConstantOp<T>",
8    op="DoubleOutOp",
9    op="FailingOperator",
10    op="IncrementOperator",
11    op="Merge2Op",
12    op="MultiplyOp",
13    op="NoOpOperator",
14    op="SingleChannelPassthroughOperator<T>",
15    op="SingleValOp",
16    op="SplitAndDoubleOp",
17    op="StreamyOperator<T>",
18    op="SinkOperator<T>",
19)]
20pub struct TestWire<T: Zero + Display + Copy + Debug + Send + Sync + PartialEq + Eq> {
21    _0: PhantomData<T>,
22}
23
24#[macro_export]
25macro_rules! test_wire_port0_into {
26    ($x:ident => $ty:ty) => {
27        <TestWireIO<i32> as PortTryInto0<$ty>>::port_try_into0($x).expect("expected to be able to wire into type")
28    }
29}
30
31#[macro_export]
32macro_rules! test_wire_port1_into {
33    ($x:ident => $ty:ty) => {
34        <TestWireIO<i32> as PortTryInto1<$ty>>::port_try_into1($x).expect("expected to be able to wire into type")
35    }
36}
37
38#[macro_export]
39macro_rules! test_wire_port2_into {
40    ($x:ident => $ty:ty) => {
41        <TestWireIO<i32> as PortTryInto2<$ty>>::port_try_into2($x).expect("expected to be able to wire into type")
42    }
43}
44
45#[macro_export]
46macro_rules! test_wire_port3_into {
47    ($x:ident => $ty:ty) => {
48        <TestWireIO<i32> as PortTryInto3<$ty>>::port_try_into3($x).expect("expected to be able to wire into type")
49    }
50}
hydro2_network/test_wire.rs

hydro2_network/
test_wire.rs
