Module plain 

Bitplane framebuffers for a 16-bit plain HUB75 interface.

All signals (row address, latch, OE, colour data) are packed into each 16-bit word – no external latch circuit is required.

Two layout variants are provided:

• frame – Plane-major: all rows for one bit-plane stored contiguously. The DMA chain sends each plane’s data separately.
• row – Row-major: all bit-planes for a single row stored contiguously. Optimized for row-by-row BCM where the inter-row gap appears only once per scan row instead of once per plane.

Both variants share the same 16-bit Entry format and pin mapping.

Hardware Requirements

Requires a parallel output peripheral capable of clocking 16 bits (though only 15 are actually used) at a time. The data is structured to directly match the HUB75 connector signals, so no external latch or address-decode hardware is needed.

HUB75 Signal Bit Mapping

Each 16-bit Entry represents the logic levels driven onto the HUB75 bus during a single pixel-clock cycle:

default (ESP32 I2S / generic)          interstate75 (RP2040/RP2350 PIO)
15 ─ (spare)                           15 ─ (spare)
14 ─ B1       Blue  – lower half       14 ─ (spare)
13 ─ G1       Green – lower half       13 ─ OE    Output-Enable / Blank
12 ─ R1       Red   – lower half       12 ─ LAT   Latch / STB
11 ─ B0       Blue  – upper half       11 ─ (spare)
10 ─ G0       Green – upper half       10 ─ E     Row address
 9 ─ R0       Red   – upper half        9 ─ D     Row address
 8 ─ OE       Output-Enable / Blank      8 ─ C     Row address
 7 ─ (spare)                             7 ─ B     Row address
 6 ─ (spare)                             6 ─ A     Row address
 5 ─ LAT      Latch / STB                5 ─ B1    Blue  – lower half
4-0 ─ A..E    Row address lines          4 ─ G1    Green – lower half
                                         3 ─ R1    Red   – lower half
                                         2 ─ B0    Blue  – upper half
                                         1 ─ G0    Green – upper half
                                         0 ─ R0    Red   – upper half

The board-specific layout is selected by the interstate75 feature; see crate::pinmap.

The pixel clock is generated by the peripheral that owns the DMA stream and is not part of the 16-bit word stored in the framebuffer.

Bitplane BCM Rendering

Each framebuffer is organised into PLANES bit-planes, one per colour bit. To produce correct brightness via Binary Code Modulation, output each plane’s data (scan it) a number of times equal to its bit-weight (2^7 for the MSB plane down to 2^0 for the LSB plane) — either with a DMA descriptor chain or by reprogramming the DMA registers per segment from a transfer-complete interrupt.

Both layout variants store planes LSB-first: plane 0 carries bit 0 and is displayed once per scan, plane 7 carries bit 7 and is displayed 128 times. Each BCM segment streams a contiguous suffix of planes, repeated just enough times to bring each plane’s total coverage to its bit-weight — halving the number of DMA transfers per scan with identical brightness. LSB-first ordering also means the first plane after an address change displays stale data with minimal visual weight, avoiding a separate primer segment. See the frame and row module documentation for the exact scan order.

See https://www.batsocks.co.uk/readme/art_bcm_1.htm for background on BCM.

Re-exports

pub use frame::DmaFrameBuffer;

Modules

frame

Plane-major bitplane framebuffer.

row

Row-major bitplane framebuffer.