ht32f523x2/adc/
lst0.rs

1#[doc = "Register `LST0` reader"]
2pub type R = crate::R<Lst0Spec>;
3#[doc = "Register `LST0` writer"]
4pub type W = crate::W<Lst0Spec>;
5#[doc = "Field `ADSEQ0` reader - ADSEQ0"]
6pub type Adseq0R = crate::FieldReader;
7#[doc = "Field `ADSEQ0` writer - ADSEQ0"]
8pub type Adseq0W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `ADSEQ1` reader - ADSEQ1"]
10pub type Adseq1R = crate::FieldReader;
11#[doc = "Field `ADSEQ1` writer - ADSEQ1"]
12pub type Adseq1W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `ADSEQ2` reader - ADSEQ2"]
14pub type Adseq2R = crate::FieldReader;
15#[doc = "Field `ADSEQ2` writer - ADSEQ2"]
16pub type Adseq2W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
17#[doc = "Field `ADSEQ3` reader - ADSEQ3"]
18pub type Adseq3R = crate::FieldReader;
19#[doc = "Field `ADSEQ3` writer - ADSEQ3"]
20pub type Adseq3W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
21impl R {
22    #[doc = "Bits 0:4 - ADSEQ0"]
23    #[inline(always)]
24    pub fn adseq0(&self) -> Adseq0R {
25        Adseq0R::new((self.bits & 0x1f) as u8)
26    }
27    #[doc = "Bits 8:12 - ADSEQ1"]
28    #[inline(always)]
29    pub fn adseq1(&self) -> Adseq1R {
30        Adseq1R::new(((self.bits >> 8) & 0x1f) as u8)
31    }
32    #[doc = "Bits 16:20 - ADSEQ2"]
33    #[inline(always)]
34    pub fn adseq2(&self) -> Adseq2R {
35        Adseq2R::new(((self.bits >> 16) & 0x1f) as u8)
36    }
37    #[doc = "Bits 24:28 - ADSEQ3"]
38    #[inline(always)]
39    pub fn adseq3(&self) -> Adseq3R {
40        Adseq3R::new(((self.bits >> 24) & 0x1f) as u8)
41    }
42}
43impl W {
44    #[doc = "Bits 0:4 - ADSEQ0"]
45    #[inline(always)]
46    #[must_use]
47    pub fn adseq0(&mut self) -> Adseq0W<Lst0Spec> {
48        Adseq0W::new(self, 0)
49    }
50    #[doc = "Bits 8:12 - ADSEQ1"]
51    #[inline(always)]
52    #[must_use]
53    pub fn adseq1(&mut self) -> Adseq1W<Lst0Spec> {
54        Adseq1W::new(self, 8)
55    }
56    #[doc = "Bits 16:20 - ADSEQ2"]
57    #[inline(always)]
58    #[must_use]
59    pub fn adseq2(&mut self) -> Adseq2W<Lst0Spec> {
60        Adseq2W::new(self, 16)
61    }
62    #[doc = "Bits 24:28 - ADSEQ3"]
63    #[inline(always)]
64    #[must_use]
65    pub fn adseq3(&mut self) -> Adseq3W<Lst0Spec> {
66        Adseq3W::new(self, 24)
67    }
68}
69#[doc = "LST0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lst0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lst0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
70pub struct Lst0Spec;
71impl crate::RegisterSpec for Lst0Spec {
72    type Ux = u32;
73}
74#[doc = "`read()` method returns [`lst0::R`](R) reader structure"]
75impl crate::Readable for Lst0Spec {}
76#[doc = "`write(|w| ..)` method takes [`lst0::W`](W) writer structure"]
77impl crate::Writable for Lst0Spec {
78    type Safety = crate::Unsafe;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
81}
82#[doc = "`reset()` method sets LST0 to value 0"]
83impl crate::Resettable for Lst0Spec {
84    const RESET_VALUE: u32 = 0;
85}
ht32f523x2/adc/lst0.rs

ht32f523x2/adc/
lst0.rs
