hrx/fabric/
capabilities.rs

1use super::*;
2
3/// Native packet representation accepted by one queue family.
4#[derive(Clone, Copy, Debug, PartialEq, Eq)]
5pub enum QueueCommand {
6    /// GPU compute/control packets.
7    Pm4,
8    /// GPU DMA packets.
9    Sdma,
10    /// HSA kernel dispatch packets.
11    Aql,
12    /// HSA packets with native metadata.
13    AqlMetadata,
14    /// XDNA establishing commands.
15    Xdna,
16    /// A representation not currently encoded by this crate.
17    Unknown(u32),
18}
19/// Passive, immutable capabilities copied from the current native provider.
20#[derive(Clone, Debug)]
21pub struct QueueCapabilities {
22    /// Dense family ordinal accepted by memory visibility queries.
23    pub ordinal: u32,
24    /// Native command representation.
25    pub command: QueueCommand,
26    /// Command-format version.
27    pub format_version: u32,
28    /// Representation-specific feature bits from the native ABI.
29    pub format_features: u64,
30    /// Host/device direct publication is available.
31    pub user_publication: bool,
32    /// Kernel-mediated publication is available.
33    pub kernel_publication: bool,
34    /// Minimum ring length in bytes.
35    pub minimum_ring_bytes: u64,
36    /// Maximum ring length in bytes.
37    pub maximum_ring_bytes: u64,
38    /// Required ring-length alignment.
39    pub ring_alignment: u64,
40    /// Queue can release writes to system memory.
41    pub system_release: bool,
42    /// Queue can acquire writes from system memory.
43    pub system_acquire: bool,
44}
45impl Endpoint {
46    /// Inspect all native queue families without opening a device or queue.
47    pub fn queue_capabilities(&self) -> Result<Vec<QueueCapabilities>> {
48        let api = self.0.instance.api.core;
49        let mut info = amdf_endpoint_info_t {
50            type_: AMDF_STRUCTURE_TYPE_ENDPOINT_INFO,
51            structure_size: size_of::<amdf_endpoint_info_t>() as u32,
52            ..Default::default()
53        };
54        check("endpoint_query_info", unsafe {
55            entry!(api, endpoint_query_info)(self.0.raw, &mut info)
56        })?;
57        (0..info.queue_family_count)
58            .map(|ordinal| {
59                let mut family = amdf_queue_family_info_t {
60                    type_: AMDF_STRUCTURE_TYPE_QUEUE_FAMILY_INFO,
61                    structure_size: size_of::<amdf_queue_family_info_t>() as u32,
62                    ..Default::default()
63                };
64                check("endpoint_query_queue_family_info", unsafe {
65                    entry!(api, endpoint_query_queue_family_info)(self.0.raw, ordinal, &mut family)
66                })?;
67                Ok(QueueCapabilities {
68                    ordinal,
69                    command: match family.command_type {
70                        AMDF_QUEUE_COMMAND_TYPE_GPU_PM4 => QueueCommand::Pm4,
71                        AMDF_QUEUE_COMMAND_TYPE_GPU_SDMA => QueueCommand::Sdma,
72                        AMDF_QUEUE_COMMAND_TYPE_GPU_AQL => QueueCommand::Aql,
73                        AMDF_QUEUE_COMMAND_TYPE_GPU_AQL_METADATA => QueueCommand::AqlMetadata,
74                        AMDF_QUEUE_COMMAND_TYPE_XDNA => QueueCommand::Xdna,
75                        unknown => QueueCommand::Unknown(unknown),
76                    },
77                    format_version: family.format_version,
78                    format_features: family.format_features,
79                    user_publication: family.publication_modes & AMDF_QUEUE_PUBLICATION_MODE_USER
80                        != 0,
81                    kernel_publication: family.publication_modes
82                        & AMDF_QUEUE_PUBLICATION_MODE_KERNEL
83                        != 0,
84                    minimum_ring_bytes: family.minimum_ring_byte_length,
85                    maximum_ring_bytes: family.maximum_ring_byte_length,
86                    ring_alignment: family.ring_byte_length_alignment,
87                    system_release: family.cache_operations
88                        & (1 << AMDF_CACHE_OPERATION_RELEASE_TO_SYSTEM)
89                        != 0,
90                    system_acquire: family.cache_operations
91                        & (1 << AMDF_CACHE_OPERATION_ACQUIRE_FROM_SYSTEM)
92                        != 0,
93                })
94            })
95            .collect()
96    }
97}
hrx/fabric/capabilities.rs

hrx/fabric/
capabilities.rs
