Module clock_cpu 

no description available

Structs

CLOCK_CPU_SPEC

no description available

Type Aliases

DIV_R

Field DIV reader - clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256

DIV_W

Field DIV writer - clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256

GLB_BUSY_R

Field GLB_BUSY reader - global busy 0: no changes pending to any clock 1: any of nodes is changing status

LOC_BUSY_R

Field LOC_BUSY reader - local busy 0: a change is pending for current node 1: current node is changing status

MUX_R

Field MUX reader - current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3

MUX_W

Field MUX writer - current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3

PRESERVE_R

Field PRESERVE reader - preserve function against global select 0: select global clock setting 1: not select global clock setting

PRESERVE_W

Field PRESERVE writer - preserve function against global select 0: select global clock setting 1: not select global clock setting

R

Register CLOCK_CPU[%s] reader

SUB0_DIV_R

Field SUB0_DIV reader - ahb bus divider, the bus clock is generated by cpu_clock/div 0: divider by 1 1: divider by 2 …

SUB0_DIV_W

Field SUB0_DIV writer - ahb bus divider, the bus clock is generated by cpu_clock/div 0: divider by 1 1: divider by 2 …

W

Register CLOCK_CPU[%s] writer