hexagon_e/
module.rs

1use error::*;
2use byteorder::{LittleEndian, ByteOrder};
3
4#[derive(Copy, Clone, Debug)]
5pub struct Module<'a> {
6    pub memory_initializers: &'a [u8], // Serialized
7    pub code: &'a [u8] // Raw opcodes & immediates
8}
9
10impl<'a> Module<'a> {
11    pub fn from_raw(mut s: &'a [u8]) -> ExecuteResult<Module<'a>> {
12        if s.len() < 4 {
13            return Err(ExecuteError::Bounds);
14        }
15        let initializers_len = LittleEndian::read_u32(s) as usize;
16        s = &s[4..];
17
18        if s.len() < initializers_len {
19            return Err(ExecuteError::Bounds);
20        }
21        let memory_initializers = &s[0..initializers_len];
22        s = &s[initializers_len..];
23
24        let code = s;
25
26        Ok(Module {
27            memory_initializers: memory_initializers,
28            code: code
29        })
30    }
31}
32
33#[derive(Copy, Clone, Debug)]
34#[repr(u8)]
35pub enum Opcode {
36    Drop = 1,
37    Dup,
38    Swap2,
39    Select,
40
41    Call,
42    Return,
43    Halt,
44
45    GetLocal,
46    SetLocal,
47    TeeLocal,
48
49    GetSlotIndirect,
50    GetSlot,
51    SetSlot,
52    ResetSlots,
53
54    NativeInvoke,
55
56    CurrentMemory,
57    GrowMemory,
58
59    Nop,
60    Unreachable,
61    NotSupported,
62
63    Jmp,
64    JmpIf,
65    JmpEither,
66    JmpTable,
67
68    I32Load,
69    I32Load8U,
70    I32Load8S,
71    I32Load16U,
72    I32Load16S,
73    I32Store,
74    I32Store8,
75    I32Store16,
76
77    I32Const,
78    I32Ctz,
79    I32Clz,
80    I32Popcnt,
81    I32Add,
82    I32Sub,
83    I32Mul,
84    I32DivU,
85    I32DivS,
86    I32RemU,
87    I32RemS,
88    I32And,
89    I32Or,
90    I32Xor,
91    I32Shl,
92    I32ShrU,
93    I32ShrS,
94    I32Rotl,
95    I32Rotr,
96
97    I32Eq,
98    I32Ne,
99    I32LtU,
100    I32LtS,
101    I32LeU,
102    I32LeS,
103    I32GtU,
104    I32GtS,
105    I32GeU,
106    I32GeS,
107
108    I32WrapI64,
109
110    I64Load,
111    I64Load8U,
112    I64Load8S,
113    I64Load16U,
114    I64Load16S,
115    I64Load32U,
116    I64Load32S,
117    I64Store,
118    I64Store8,
119    I64Store16,
120    I64Store32,
121
122    I64Const,
123    I64Ctz,
124    I64Clz,
125    I64Popcnt,
126    I64Add,
127    I64Sub,
128    I64Mul,
129    I64DivU,
130    I64DivS,
131    I64RemU,
132    I64RemS,
133    I64And,
134    I64Or,
135    I64Xor,
136    I64Shl,
137    I64ShrU,
138    I64ShrS,
139    I64Rotl,
140    I64Rotr,
141
142    I64Eq,
143    I64Ne,
144    I64LtU,
145    I64LtS,
146    I64LeU,
147    I64LeS,
148    I64GtU,
149    I64GtS,
150    I64GeU,
151    I64GeS,
152
153    I64ExtendI32U,
154    I64ExtendI32S,
155
156    Never
157}
158
159impl Opcode {
160    #[inline]
161    pub fn from_raw(v: u8) -> ExecuteResult<Opcode> {
162        if v > 0 && v < Opcode::Never as u8 {
163            Ok(unsafe { ::core::mem::transmute(v) })
164        } else {
165            Err(ExecuteError::IllegalOpcode)
166        }
167    }
168}
hexagon_e/module.rs

hexagon_e/
module.rs
