hermes_simd_types/
lib.rs

1//! Monomorphized vector register types for the hermes-simd workspace.
2//!
3//! Provides compile-time configured type aliases that map to target-optimal registers
4//! and explicit aliases for each hardware backend.
5
6#![cfg_attr(not(feature = "std"), no_std)]
7#![deny(missing_docs)]
8
9pub use hermes_simd_core::scalar::{Bf16, Bf4, Bf8, F16, F32, F4, F64, F8, I16, I32, I8};
10pub use hermes_simd_core::view::{Mask, Vector};
11pub use hermes_simd_intrinsics::{Avx2, Avx512, Neon, Scalar};
12
13// -----------------------------------------------------------------------------
14// Preferred Architecture Typestate Selection
15// -----------------------------------------------------------------------------
16
17/// The optimal target architecture typestate compiled for the current host CPU target.
18#[cfg(all(
19    any(target_arch = "x86", target_arch = "x86_64"),
20    target_feature = "avx512f"
21))]
22pub type PreferredArch = hermes_simd_intrinsics::Avx512;
23
24/// The optimal target architecture typestate compiled for the current host CPU target.
25#[cfg(all(
26    any(target_arch = "x86", target_arch = "x86_64"),
27    not(target_feature = "avx512f"),
28    target_feature = "avx2"
29))]
30pub type PreferredArch = hermes_simd_intrinsics::Avx2;
31
32/// The optimal target architecture typestate compiled for the current host CPU target.
33#[cfg(all(
34    any(target_arch = "x86", target_arch = "x86_64"),
35    not(target_feature = "avx512f"),
36    not(target_feature = "avx2")
37))]
38pub type PreferredArch = hermes_simd_intrinsics::Scalar;
39
40/// The optimal target architecture typestate compiled for the current host CPU target.
41#[cfg(target_arch = "aarch64")]
42pub type PreferredArch = hermes_simd_intrinsics::Neon;
43
44/// The optimal target architecture typestate compiled for the current host CPU target.
45#[cfg(not(any(target_arch = "x86", target_arch = "x86_64", target_arch = "aarch64")))]
46pub type PreferredArch = hermes_simd_intrinsics::Scalar;
47
48// -----------------------------------------------------------------------------
49// Generic Wrappers
50// -----------------------------------------------------------------------------
51
52/// Generic f32 SIMD vector register.
53pub type VectorF32<A> = Vector<F32, A>;
54/// Generic f64 SIMD vector register.
55pub type VectorF64<A> = Vector<F64, A>;
56/// Generic standard f16 SIMD vector register.
57pub type VectorF16<A> = Vector<F16, A>;
58/// Generic bfloat16 SIMD vector register.
59pub type VectorBf16<A> = Vector<Bf16, A>;
60/// Generic bfloat8 SIMD vector register.
61pub type VectorBf8<A> = Vector<Bf8, A>;
62/// Generic bfloat4 SIMD vector register.
63pub type VectorBf4<A> = Vector<Bf4, A>;
64/// Generic float8 SIMD vector register.
65pub type VectorF8<A> = Vector<F8, A>;
66/// Generic float4 SIMD vector register.
67pub type VectorF4<A> = Vector<F4, A>;
68/// Generic i8 SIMD vector register.
69pub type VectorI8<A> = Vector<I8, A>;
70/// Generic i16 SIMD vector register.
71pub type VectorI16<A> = Vector<I16, A>;
72/// Generic i32 SIMD vector register.
73pub type VectorI32<A> = Vector<I32, A>;
74
75/// Generic f32 SIMD lane selection mask.
76pub type MaskF32<A> = Mask<F32, A>;
77/// Generic f64 SIMD lane selection mask.
78pub type MaskF64<A> = Mask<F64, A>;
79/// Generic standard f16 SIMD lane selection mask.
80pub type MaskF16<A> = Mask<F16, A>;
81/// Generic bfloat16 SIMD lane selection mask.
82pub type MaskBf16<A> = Mask<Bf16, A>;
83/// Generic bfloat8 SIMD lane selection mask.
84pub type MaskBf8<A> = Mask<Bf8, A>;
85/// Generic bfloat4 SIMD lane selection mask.
86pub type MaskBf4<A> = Mask<Bf4, A>;
87/// Generic float8 SIMD lane selection mask.
88pub type MaskF8<A> = Mask<F8, A>;
89/// Generic float4 SIMD lane selection mask.
90pub type MaskF4<A> = Mask<F4, A>;
91/// Generic i8 SIMD lane selection mask.
92pub type MaskI8<A> = Mask<I8, A>;
93/// Generic i16 SIMD lane selection mask.
94pub type MaskI16<A> = Mask<I16, A>;
95/// Generic i32 SIMD lane selection mask.
96pub type MaskI32<A> = Mask<I32, A>;
97
98// -----------------------------------------------------------------------------
99// Preferred SIMD Target Aliases
100// -----------------------------------------------------------------------------
101
102/// Optimal f32 SIMD register compiled for the host.
103pub type SimdF32 = Vector<F32, PreferredArch>;
104/// Optimal f64 SIMD register compiled for the host.
105pub type SimdF64 = Vector<F64, PreferredArch>;
106/// Optimal f16 SIMD register compiled for the host.
107pub type SimdF16 = Vector<F16, PreferredArch>;
108/// Optimal bfloat16 SIMD register compiled for the host.
109pub type SimdBf16 = Vector<Bf16, PreferredArch>;
110/// Optimal bfloat8 SIMD register compiled for the host.
111pub type SimdBf8 = Vector<Bf8, PreferredArch>;
112/// Optimal bfloat4 SIMD register compiled for the host.
113pub type SimdBf4 = Vector<Bf4, PreferredArch>;
114/// Optimal float8 SIMD register compiled for the host.
115pub type SimdF8 = Vector<F8, PreferredArch>;
116/// Optimal float4 SIMD register compiled for the host.
117pub type SimdF4 = Vector<F4, PreferredArch>;
118/// Optimal i8 SIMD register compiled for the host.
119pub type SimdI8 = Vector<I8, PreferredArch>;
120/// Optimal i16 SIMD register compiled for the host.
121pub type SimdI16 = Vector<I16, PreferredArch>;
122/// Optimal i32 SIMD register compiled for the host.
123pub type SimdI32 = Vector<I32, PreferredArch>;
124
125/// Optimal f32 SIMD mask register compiled for the host.
126pub type SimdMaskF32 = Mask<F32, PreferredArch>;
127/// Optimal f64 SIMD mask register compiled for the host.
128pub type SimdMaskF64 = Mask<F64, PreferredArch>;
129/// Optimal f16 SIMD mask register compiled for the host.
130pub type SimdMaskF16 = Mask<F16, PreferredArch>;
131/// Optimal bfloat16 SIMD mask register compiled for the host.
132pub type SimdMaskBf16 = Mask<Bf16, PreferredArch>;
133/// Optimal bfloat8 SIMD mask register compiled for the host.
134pub type SimdMaskBf8 = Mask<Bf8, PreferredArch>;
135/// Optimal bfloat4 SIMD mask register compiled for the host.
136pub type SimdMaskBf4 = Mask<Bf4, PreferredArch>;
137/// Optimal float8 SIMD mask register compiled for the host.
138pub type SimdMaskF8 = Mask<F8, PreferredArch>;
139/// Optimal float4 SIMD mask register compiled for the host.
140pub type SimdMaskF4 = Mask<F4, PreferredArch>;
141/// Optimal i8 SIMD mask register compiled for the host.
142pub type SimdMaskI8 = Mask<I8, PreferredArch>;
143/// Optimal i16 SIMD mask register compiled for the host.
144pub type SimdMaskI16 = Mask<I16, PreferredArch>;
145/// Optimal i32 SIMD mask register compiled for the host.
146pub type SimdMaskI32 = Mask<I32, PreferredArch>;
147
148// -----------------------------------------------------------------------------
149// Concrete Target-Bound Register Aliases
150// -----------------------------------------------------------------------------
151
152/// Concrete 1-element scalar emulation f32 vector register.
153pub type ScalarF32 = Vector<F32, Scalar>;
154/// Concrete 1-element scalar emulation f64 vector register.
155pub type ScalarF64 = Vector<F64, Scalar>;
156/// Concrete 1-element scalar emulation f16 vector register.
157pub type ScalarF16 = Vector<F16, Scalar>;
158/// Concrete 1-element scalar emulation bfloat16 vector register.
159pub type ScalarBf16 = Vector<Bf16, Scalar>;
160/// Concrete 1-element scalar emulation bfloat8 vector register.
161pub type ScalarBf8 = Vector<Bf8, Scalar>;
162/// Concrete 1-element scalar emulation bfloat4 vector register.
163pub type ScalarBf4 = Vector<Bf4, Scalar>;
164/// Concrete 1-element scalar emulation float8 vector register.
165pub type ScalarF8 = Vector<F8, Scalar>;
166/// Concrete 1-element scalar emulation float4 vector register.
167pub type ScalarF4 = Vector<F4, Scalar>;
168/// Concrete 1-element scalar emulation i8 vector register.
169pub type ScalarI8 = Vector<I8, Scalar>;
170/// Concrete 1-element scalar emulation i16 vector register.
171pub type ScalarI16 = Vector<I16, Scalar>;
172/// Concrete 1-element scalar emulation i32 vector register.
173pub type ScalarI32 = Vector<I32, Scalar>;
174
175/// Concrete 1-element scalar emulation f32 mask register.
176pub type ScalarMaskF32 = Mask<F32, Scalar>;
177/// Concrete 1-element scalar emulation f64 mask register.
178pub type ScalarMaskF64 = Mask<F64, Scalar>;
179
180#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
181pub use x86_aliases::*;
182
183#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
184mod x86_aliases {
185    use super::*;
186
187    // AVX2 Vector types
188    /// Concrete AVX2 f32 vector register (8 lanes).
189    pub type Avx2F32 = Vector<F32, Avx2>;
190    /// Concrete AVX2 f64 vector register (4 lanes).
191    pub type Avx2F64 = Vector<F64, Avx2>;
192    /// Concrete AVX2 standard f16 vector register (16 lanes).
193    pub type Avx2F16 = Vector<F16, Avx2>;
194    /// Concrete AVX2 bfloat16 vector register (16 lanes).
195    pub type Avx2Bf16 = Vector<Bf16, Avx2>;
196    /// Concrete AVX2 bfloat8 vector register (32 lanes).
197    pub type Avx2Bf8 = Vector<Bf8, Avx2>;
198    /// Concrete AVX2 bfloat4 vector register (32 lanes).
199    pub type Avx2Bf4 = Vector<Bf4, Avx2>;
200    /// Concrete AVX2 float8 vector register (32 lanes).
201    pub type Avx2F8 = Vector<F8, Avx2>;
202    /// Concrete AVX2 float4 vector register (32 lanes).
203    pub type Avx2F4 = Vector<F4, Avx2>;
204    /// Concrete AVX2 i8 vector register (32 lanes).
205    pub type Avx2I8 = Vector<I8, Avx2>;
206    /// Concrete AVX2 i16 vector register (16 lanes).
207    pub type Avx2I16 = Vector<I16, Avx2>;
208    /// Concrete AVX2 i32 vector register (8 lanes).
209    pub type Avx2I32 = Vector<I32, Avx2>;
210
211    // AVX2 Mask types
212    /// Concrete AVX2 f32 mask register (8 lanes).
213    pub type Avx2MaskF32 = Mask<F32, Avx2>;
214    /// Concrete AVX2 f64 mask register (4 lanes).
215    pub type Avx2MaskF64 = Mask<F64, Avx2>;
216    /// Concrete AVX2 f16 mask register (16 lanes).
217    pub type Avx2MaskF16 = Mask<F16, Avx2>;
218    /// Concrete AVX2 bfloat16 mask register (16 lanes).
219    pub type Avx2MaskBf16 = Mask<Bf16, Avx2>;
220
221    // AVX-512 Vector types
222    /// Concrete AVX-512 f32 vector register (16 lanes).
223    pub type Avx512F32 = Vector<F32, Avx512>;
224    /// Concrete AVX-512 f64 vector register (8 lanes).
225    pub type Avx512F64 = Vector<F64, Avx512>;
226    /// Concrete AVX-512 standard f16 vector register (32 lanes).
227    pub type Avx512F16 = Vector<F16, Avx512>;
228    /// Concrete AVX-512 bfloat16 vector register (32 lanes).
229    pub type Avx512Bf16 = Vector<Bf16, Avx512>;
230    /// Concrete AVX-512 bfloat8 vector register (64 lanes).
231    pub type Avx512Bf8 = Vector<Bf8, Avx512>;
232    /// Concrete AVX-512 bfloat4 vector register (64 lanes).
233    pub type Avx512Bf4 = Vector<Bf4, Avx512>;
234    /// Concrete AVX-512 float8 vector register (64 lanes).
235    pub type Avx512F8 = Vector<F8, Avx512>;
236    /// Concrete AVX-512 float4 vector register (64 lanes).
237    pub type Avx512F4 = Vector<F4, Avx512>;
238    /// Concrete AVX-512 i8 vector register (64 lanes).
239    pub type Avx512I8 = Vector<I8, Avx512>;
240    /// Concrete AVX-512 i16 vector register (32 lanes).
241    pub type Avx512I16 = Vector<I16, Avx512>;
242    /// Concrete AVX-512 i32 vector register (16 lanes).
243    pub type Avx512I32 = Vector<I32, Avx512>;
244
245    // AVX-512 Mask types
246    /// Concrete AVX-512 f32 mask register (16 lanes).
247    pub type Avx512MaskF32 = Mask<F32, Avx512>;
248    /// Concrete AVX-512 f64 mask register (8 lanes).
249    pub type Avx512MaskF64 = Mask<F64, Avx512>;
250    /// Concrete AVX-512 f16 mask register (32 lanes).
251    pub type Avx512MaskF16 = Mask<F16, Avx512>;
252    /// Concrete AVX-512 bfloat16 mask register (32 lanes).
253    pub type Avx512MaskBf16 = Mask<Bf16, Avx512>;
254}
255
256#[cfg(target_arch = "aarch64")]
257pub use aarch64_aliases::*;
258
259#[cfg(target_arch = "aarch64")]
260mod aarch64_aliases {
261    use super::*;
262
263    // NEON Vector types
264    /// Concrete NEON f32 vector register (4 lanes).
265    pub type NeonF32 = Vector<F32, Neon>;
266    /// Concrete NEON f64 vector register (2 lanes).
267    pub type NeonF64 = Vector<F64, Neon>;
268    /// Concrete NEON standard f16 vector register (8 lanes).
269    pub type NeonF16 = Vector<F16, Neon>;
270    /// Concrete NEON bfloat16 vector register (8 lanes).
271    pub type NeonBf16 = Vector<Bf16, Neon>;
272    /// Concrete NEON bfloat8 vector register (16 lanes).
273    pub type NeonBf8 = Vector<Bf8, Neon>;
274    /// Concrete NEON bfloat4 vector register (16 lanes).
275    pub type NeonBf4 = Vector<Bf4, Neon>;
276    /// Concrete NEON float8 vector register (16 lanes).
277    pub type NeonF8 = Vector<F8, Neon>;
278    /// Concrete NEON float4 vector register (16 lanes).
279    pub type NeonF4 = Vector<F4, Neon>;
280    /// Concrete NEON i8 vector register (16 lanes).
281    pub type NeonI8 = Vector<I8, Neon>;
282    /// Concrete NEON i16 vector register (8 lanes).
283    pub type NeonI16 = Vector<I16, Neon>;
284    /// Concrete NEON i32 vector register (4 lanes).
285    pub type NeonI32 = Vector<I32, Neon>;
286
287    // NEON Mask types
288    /// Concrete NEON f32 mask register (4 lanes).
289    pub type NeonMaskF32 = Mask<F32, Neon>;
290    /// Concrete NEON f64 mask register (2 lanes).
291    pub type NeonMaskF64 = Mask<F64, Neon>;
292    /// Concrete NEON f16 mask register (8 lanes).
293    pub type NeonMaskF16 = Mask<F16, Neon>;
294    /// Concrete NEON bfloat16 mask register (8 lanes).
295    pub type NeonMaskBf16 = Mask<Bf16, Neon>;
296}
hermes_simd_types/lib.rs

hermes_simd_types/
lib.rs
