1use embedded_hal::blocking::delay::{DelayMs, DelayUs};
2use embedded_hal::digital::v2::OutputPin;
3
4use crate::{
5 bus::DataBus,
6 error::{Error, Result},
7};
8
9pub struct EightBitBus<
10 RS: OutputPin,
11 EN: OutputPin,
12 D0: OutputPin,
13 D1: OutputPin,
14 D2: OutputPin,
15 D3: OutputPin,
16 D4: OutputPin,
17 D5: OutputPin,
18 D6: OutputPin,
19 D7: OutputPin,
20> {
21 rs: RS,
22 en: EN,
23 d0: D0,
24 d1: D1,
25 d2: D2,
26 d3: D3,
27 d4: D4,
28 d5: D5,
29 d6: D6,
30 d7: D7,
31}
32
33impl<
34 RS: OutputPin,
35 EN: OutputPin,
36 D0: OutputPin,
37 D1: OutputPin,
38 D2: OutputPin,
39 D3: OutputPin,
40 D4: OutputPin,
41 D5: OutputPin,
42 D6: OutputPin,
43 D7: OutputPin,
44 > EightBitBus<RS, EN, D0, D1, D2, D3, D4, D5, D6, D7>
45{
46 pub fn from_pins(
47 rs: RS,
48 en: EN,
49 d0: D0,
50 d1: D1,
51 d2: D2,
52 d3: D3,
53 d4: D4,
54 d5: D5,
55 d6: D6,
56 d7: D7,
57 ) -> EightBitBus<RS, EN, D0, D1, D2, D3, D4, D5, D6, D7> {
58 EightBitBus {
59 rs,
60 en,
61 d0,
62 d1,
63 d2,
64 d3,
65 d4,
66 d5,
67 d6,
68 d7,
69 }
70 }
71
72 fn set_bus_bits(&mut self, data: u8) -> Result<()> {
73 let db0: bool = (0b0000_0001 & data) != 0;
74 let db1: bool = (0b0000_0010 & data) != 0;
75 let db2: bool = (0b0000_0100 & data) != 0;
76 let db3: bool = (0b0000_1000 & data) != 0;
77 let db4: bool = (0b0001_0000 & data) != 0;
78 let db5: bool = (0b0010_0000 & data) != 0;
79 let db6: bool = (0b0100_0000 & data) != 0;
80 let db7: bool = (0b1000_0000 & data) != 0;
81
82 if db0 {
83 self.d0.set_high().map_err(|_| Error)?;
84 } else {
85 self.d0.set_low().map_err(|_| Error)?;
86 }
87
88 if db1 {
89 self.d1.set_high().map_err(|_| Error)?;
90 } else {
91 self.d1.set_low().map_err(|_| Error)?;
92 }
93
94 if db2 {
95 self.d2.set_high().map_err(|_| Error)?;
96 } else {
97 self.d2.set_low().map_err(|_| Error)?;
98 }
99
100 if db3 {
101 self.d3.set_high().map_err(|_| Error)?;
102 } else {
103 self.d3.set_low().map_err(|_| Error)?;
104 }
105
106 if db4 {
107 self.d4.set_high().map_err(|_| Error)?;
108 } else {
109 self.d4.set_low().map_err(|_| Error)?;
110 }
111
112 if db5 {
113 self.d5.set_high().map_err(|_| Error)?;
114 } else {
115 self.d5.set_low().map_err(|_| Error)?;
116 }
117
118 if db6 {
119 self.d6.set_high().map_err(|_| Error)?;
120 } else {
121 self.d6.set_low().map_err(|_| Error)?;
122 }
123
124 if db7 {
125 self.d7.set_high().map_err(|_| Error)?;
126 } else {
127 self.d7.set_low().map_err(|_| Error)?;
128 }
129
130 Ok(())
131 }
132}
133
134impl<
135 RS: OutputPin,
136 EN: OutputPin,
137 D0: OutputPin,
138 D1: OutputPin,
139 D2: OutputPin,
140 D3: OutputPin,
141 D4: OutputPin,
142 D5: OutputPin,
143 D6: OutputPin,
144 D7: OutputPin,
145 > DataBus for EightBitBus<RS, EN, D0, D1, D2, D3, D4, D5, D6, D7>
146{
147 fn write<D: DelayUs<u16> + DelayMs<u8>>(
148 &mut self,
149 byte: u8,
150 data: bool,
151 delay: &mut D,
152 ) -> Result<()> {
153 if data {
154 self.rs.set_high().map_err(|_| Error)?;
155 } else {
156 self.rs.set_low().map_err(|_| Error)?;
157 }
158
159 self.set_bus_bits(byte)?;
160
161 self.en.set_high().map_err(|_| Error)?;
162 delay.delay_ms(2u8);
163 self.en.set_low().map_err(|_| Error)?;
164
165 if data {
166 self.rs.set_low().map_err(|_| Error)?;
167 }
168
169 Ok(())
170 }
171}