hd44780_controller/command/
set_ddram_address.rs

1use crate::device::*;
2
3use super::*;
4
5#[derive(Clone, Debug, Eq, PartialEq)]
6pub struct SetDDRamAddress(pub u8);
7
8impl SetDDRamAddress {
9    fn code(&self) -> u8 {
10        0x80 | (self.0 & 0x7f)
11    }
12}
13
14impl SyncCommand for SetDDRamAddress {
15    type Ret = ();
16
17    type Err = super::Error;
18
19    fn execute<D: SyncDevice + ?Sized>(&self, dev: &mut D) -> Result<Self::Ret, Self::Err> {
20        dev.write_byte(RegisterSelectMode::Command, self.code())
21            .map_err(|_| super::Error::DeviceError)?;
22        dev.delay_us(50);
23
24        Ok(())
25    }
26}
27
28#[cfg(feature = "async")]
29#[cfg_attr(docsrs, doc(cfg(feature = "async")))]
30impl AsyncCommand for SetDDRamAddress {
31    type Ret = ();
32
33    type Err = super::Error;
34
35    async fn execute_async<D: AsyncDevice + ?Sized>(
36        &self,
37        dev: &mut D,
38    ) -> Result<Self::Ret, Self::Err> {
39        dev.write_byte_async(RegisterSelectMode::Command, self.code())
40            .await
41            .map_err(|_| super::Error::DeviceError)?;
42        dev.delay_us_async(50).await;
43
44        Ok(())
45    }
46}