Crate gsim

High speed digital logic simulation

Example

use gsim::*;
use std::num::NonZeroU8;

let mut builder = SimulatorBuilder::default();

// Add wires and components to the simulation
let wire_width = NonZeroU8::new(1).unwrap();
let input_a = builder.add_wire(wire_width).unwrap();
let input_b = builder.add_wire(wire_width).unwrap();
let output = builder.add_wire(wire_width).unwrap();
// The gate ID is not usefull to us because we don't intend on reading its data
let _gate = builder.add_and_gate(&[input_a, input_b], output).unwrap();

// Create the simulation
let mut sim = builder.build();

// Manually drive the input wires
sim.set_wire_drive(input_a, &LogicState::from_bool(true)).unwrap();
sim.set_wire_drive(input_b, &LogicState::from_bool(false)).unwrap();

// Run the simulation
const MAX_STEPS: u64 = 2;
match sim.run_sim(MAX_STEPS) {
    SimulationRunResult::Ok => {}
    SimulationRunResult::MaxStepsReached => panic!("simulation did not settle within allowed steps"),
    SimulationRunResult::Err(err) => panic!("simulation error: {err:?}"),
}

// Make sure we got the expected result
let output_state = sim.get_wire_state(output).unwrap();
assert!(output_state.eq(&LogicState::from_bool(false), wire_width));

Modules

import

Import circuits from various formats

Macros

bits

Constructs a logic state from a list of bits (most significant bit first)

Structs

AllocationSize

The size of a memory allocation

ComponentId

A unique identifier for a component inside a simulation

InvalidComponentIdError

A specified component ID was not part of the simulation

InvalidWireIdError

A specified wire ID was not part of the simulation

LogicState

A logic state of arbitrary bit width

SimulationErrors

Contains data of all errors that occurred in a simulation

SimulationStats

Memory usage statistics of a simulation

Simulator

A digital circuit simulator

SimulatorBuilder

Builds a simulator

Timescale

The timescale in a VCD file

WireId

A unique identifier for a wire inside a simulation

Enums

AddComponentError

Errors that can occur when adding a component to a simulator

ClockPolarity

Defines the polarity of a clock signal

ComponentData

Contains mutable data of a component

LogicBitState

The logic state of a single bit

SimulationRunResult

The result of running a simulation

Traits

Id

An ID type

Type Aliases

AddComponentResult

The result of adding a component to a simulator