Expand description
Intel Linux backend — hand-rolled std::fs readers over sysfs/fdinfo, no library
linkage (no Level Zero, no IGCL: per docs/research/02 their Linux coverage is gappy
and root-gated; plain fdinfo+sysfs is the strong path).
The defining caveat: i915 and xe are two different worlds (research 02). Same
vendor, two in-tree drivers, different fdinfo keys AND different sysfs freq layouts —
every read below is dispatched on a per-device [Dialect] detected from the uevent:
- i915 (Gen9 → Meteor Lake, DG2 default): fdinfo
drm-engine-*cumulative busy-ns (kernel 5.19+), per-process memory regions namedlocal0/system0(6.8+), card-levelgt_*_freq_mhzfiles, dGPU-onlylmem_total_bytes, hwmon package temp ontemp1_input(6.12+). - xe (Lunar Lake, Battlemage+): fdinfo
drm-cycles-*/drm-total-cycles-*GT-clock counters (6.11+), memory regions namedvram0/system/gtt(6.8+),device/tile0/gt0/freq0/*freq files, NO VRAM-total sysfs at all, hwmon package temp ontemp2_input— there is NO temp1, and temp3 is the VRAM sensor (6.15+).
Per the domain rules in CLAUDE.md:
- Every path derives from a root-dir parameter (
with_root), so the whole backend runs against committed fixture trees;init()is justwith_root("/"). - A missing file or unparsable value is
None, never a failure — an iGPU has NO hwmon at all, so temp/power/fan absence is the NORMAL case, not a broken device. hwmon itself is effectively dGPU-only and recent-kernel-gated (i915 fan/temp 6.12+; xe temps 6.15+, fans 6.16+). - Device-level utilization is deliberately
None: the i915/xe perf PMU needs root/CAP_PERFMON (intel_gpu_top’s infamous “Failed to initialize PMU”; the xe PMU only exists since 6.15), and summing fdinfo across clients we may not be able to see would understate — an invented number is worse than an honest absence. - The xe per-process utilization math is NOT the i915 math: Δbusy-cycles over
Δtotal-cycles, never over wall time — see [
cycles_util_pct]. - Other users’ fdinfo needs root/CAP_SYS_PTRACE, so unprivileged runs carry an
honest “your processes only”
process_hint(same model as the AMD backend).