Enum gpcas_cpu_model::component_config::CacheType

pub enum CacheType {
    Multiplexed(usize),
    MultiPorted(usize),
    SinglePorted,
}

How a cache handles its CPU side ports.

Variants

Multiplexed(usize)

Has multiple ports, only one port can access the cache in any clock cycle. Priority is in descending order.

Tuple Fields of Multiplexed

0: usize

MultiPorted(usize)

Has multiple ports, each port can access the cache concurrently.

Tuple Fields of MultiPorted

0: usize

SinglePorted

Has a single port.

Trait Implementations

impl<'de> Deserialize<'de> for CacheType

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error> where
    __D: Deserializer<'de>, 

Deserialize this value from the given Serde deserializer.

impl PartialEq<CacheType> for CacheType

fn eq(&self, other: &CacheType) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &CacheType) -> bool

This method tests for !=.

impl Serialize for CacheType

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error> where
    __S: Serializer, 

Serialize this value into the given Serde serializer.

impl StructuralPartialEq for CacheType