Crate gmcrypto_simd

Expand description

SIMD backends for gmcrypto-core (v0.5 W4 phase 2 / v0.6 W6).

This crate quarantines the unavoidable SIMD unsafe (AVX2 intrinsics on x86_64, NEON on aarch64) so that gmcrypto-core itself can keep unsafe_code = "forbid". The posture mirrors the established gmcrypto-c precedent (FFI shim with unsafe_code = "warn").

The crate exposes a small Rust-internal API surface only (no raw pointers, no C ABI). It is rlib-only; the single C-ABI surface for downstream callers remains gmcrypto-c.

§v0.5 W4 phase 2 scope

x86_64 AVX2 8-way packed bitsliced SM4 S-box (sm4::sbox_x8::sbox_x8), with runtime AVX2 detection via the cpufeatures crate and silent scalar fallback on non-AVX2 CPUs. 8 input bytes occupy the low lanes of the 256-bit register; the upper 24 lanes are unused.

§v0.6 W6 (phase 3) scope

x86_64 AVX2 32-byte full-width packed bitsliced S-box (sm4::sbox_x32::sbox_x32). The intended consumer is an 8-block CBC-decrypt batch fanout in gmcrypto-core (8 SM4 blocks × 4 tau bytes per round = 32 bytes per call, zero wasted lanes).
aarch64 NEON 16-byte packed bitsliced S-box (sm4::sbox_x16::sbox_x16). NEON is the architectural baseline on aarch64 (Q5.12 / Q6.3 of the v0.5 / v0.6 scope docs); compile-time gated, no runtime detect.

Re-exports§

pub use ghash::ghash_mul;

Modules§

ghash: GHASH multiplication in GF(2^128) / (x^128 + x^7 + x^2 + x + 1).
sm4: SM4 SIMD backends.

Functions§

has_avx2: Returns true if the host CPU supports AVX2 and the running translation unit may dispatch into AVX2 intrinsics.
has_pclmulqdq: Returns true if the host CPU supports the PCLMULQDQ carryless- multiply instruction (Intel Westmere+ / AMD Bulldozer+, 2010+).
has_pmull: Returns true if the host aarch64 CPU supports the ARMv8.0 Crypto Extensions PMULL64 instruction (vmull_p64).