gdt_cpus/cpu/
socket_info.rs

1use super::{CacheInfo, CoreInfo};
2
3/// Represents information about a single CPU socket (physical CPU package).
4///
5/// A CPU socket is a physical connector on a motherboard that houses a CPU.
6/// Multi-socket systems have more than one physical CPU. This structure
7/// details the cores contained within a socket and any caches shared at the socket level (e.g., L3 cache).
8#[derive(Debug, Clone)]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10pub struct SocketInfo {
11    /// A unique identifier for this CPU socket.
12    ///
13    /// For single-socket systems, this will typically be 0.
14    pub id: usize,
15    /// A list of all physical cores belonging to this socket.
16    ///
17    /// Each `CoreInfo` in this vector provides detailed information about a specific core.
18    pub cores: Vec<CoreInfo>,
19    /// Information about the L3 cache, if present and detected for this socket.
20    ///
21    /// The L3 cache (Last-Level Cache or LLC in many contexts) is typically shared
22    /// among all cores within the same physical CPU socket.
23    pub l3_cache: Option<CacheInfo>,
24}
gdt_cpus/cpu/socket_info.rs

gdt_cpus/cpu/
socket_info.rs
