gdt_cpus/cpu/
l3_domain.rs

1use crate::AffinityMask;
2
3/// A set of cores sharing one L3 cache instance.
4///
5/// On chiplet AMD parts a domain is a CCD (a 5950X has two 32 MiB domains on
6/// one socket), on hybrid Intel the E-core clusters form their own domains,
7/// and on X3D-style parts ONE domain carries the big cache. Cross-domain
8/// core-to-core latency is significantly higher than within a domain, so this
9/// is the granularity at which games should place cooperating threads.
10///
11/// Domains are content-keyed during detection (by the lowest member LP of the
12/// cache's shared set) - never attributed per socket and never deduplicated by
13/// size, both of which silently collapse multi-CCD parts into one domain.
14#[derive(Debug, Clone)]
15#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
16pub struct L3Domain {
17    /// Size of this L3 instance in bytes.
18    pub size_bytes: u64,
19    /// The LPs (OS ids) sharing this L3 instance.
20    pub mask: AffinityMask,
21    /// Physical cores in this domain (SMT siblings counted once).
22    pub core_count: u16,
23}
gdt_cpus/cpu/l3_domain.rs

gdt_cpus/cpu/
l3_domain.rs
