gdt_cpus/cpu/
features.rs

1use bitflags::bitflags;
2
3#[cfg(target_arch = "x86_64")]
4bitflags! {
5    /// Represents a set of CPU features and instruction set extensions available on an x86_64 architecture.
6    ///
7    /// These flags indicate hardware support for various SIMD (Single Instruction, Multiple Data)
8    /// extensions, cryptographic accelerators, and other specialized instructions.
9    /// Applications can query these flags to optimize performance by using the most advanced
10    /// instruction sets supported by the CPU.
11    ///
12    /// The specific flags are derived from CPUID instruction results.
13    #[derive(Default, Debug, Clone, Copy, PartialEq, Eq, Hash)]
14    #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
15    #[cfg_attr(feature = "serde", serde(transparent))]
16    pub struct CpuFeatures: u32 {
17        /// MMX (MultiMedia eXtensions) support.
18        const MMX       = 0x00000001;
19        /// SSE (Streaming SIMD Extensions) support.
20        const SSE       = 0x00000002;
21        /// SSE2 (Streaming SIMD Extensions 2) support.
22        const SSE2      = 0x00000004;
23        /// SSE3 (Streaming SIMD Extensions 3) support.
24        const SSE3      = 0x00000008;
25        /// SSSE3 (Supplemental Streaming SIMD Extensions 3) support.
26        const SSSE3     = 0x00000010;
27        /// SSE4.1 (Streaming SIMD Extensions 4.1) support.
28        const SSE4_1    = 0x00000020;
29        /// SSE4.2 (Streaming SIMD Extensions 4.2) support.
30        const SSE4_2    = 0x00000040;
31        /// FMA3 (Fused Multiply-Add 3-operand) support.
32        const FMA3      = 0x00000080;
33        /// AVX (Advanced Vector Extensions) support.
34        const AVX       = 0x00000100;
35        /// AVX2 (Advanced Vector Extensions 2) support.
36        const AVX2      = 0x00000200;
37        /// AVX-512 Foundation support.
38        const AVX512F   = 0x00000400;
39        /// AVX-512 Byte and Word Instructions support.
40        const AVX512BW  = 0x00000800;
41        /// AVX-512 Conflict Detection Instructions support.
42        const AVX512CD  = 0x00001000;
43        /// AVX-512 Doubleword and Quadword Instructions support.
44        const AVX512DQ  = 0x00002000;
45        /// AVX-512 Vector Length Extensions support.
46        const AVX512VL  = 0x00004000;
47        /// AES (Advanced Encryption Standard) hardware acceleration support.
48        const AES       = 0x00008000;
49        /// SHA (Secure Hash Algorithm) hardware acceleration support.
50        const SHA       = 0x00010000;
51        /// CRC32 (Cyclic Redundancy Check) hardware acceleration support.
52        const CRC32     = 0x00020000;
53    }
54}
55
56#[cfg(target_arch = "aarch64")]
57bitflags! {
58    /// Represents a set of CPU features and instruction set extensions available on an AArch64 architecture.
59    ///
60    /// These flags indicate hardware support for various SIMD extensions (NEON, SVE),
61    /// cryptographic accelerators, and other specialized instructions.
62    /// Applications can query these flags to optimize performance.
63    ///
64    /// The specific flags are typically derived from system registers (e.g., ID_AA64ISAR0_EL1).
65    #[derive(Default, Debug, Clone, Copy, PartialEq, Eq, Hash)]
66    #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
67    #[cfg_attr(feature = "serde", serde(transparent))]
68    pub struct CpuFeatures: u32 {
69        /// NEON (Advanced SIMD) support.
70        const NEON      = 0x00000001;
71        /// SVE (Scalable Vector Extension) support.
72        const SVE       = 0x00000002;
73        /// AES (Advanced Encryption Standard) hardware acceleration support.
74        const AES       = 0x00000004;
75        /// SHA (Secure Hash Algorithm) hardware acceleration support (SHA1, SHA256, SHA512).
76        const SHA       = 0x00000008; // Might need to be more granular (SHA1, SHA2, SHA3, SHA512)
77        /// CRC32 (Cyclic Redundancy Check) hardware acceleration support.
78        const CRC32     = 0x00000010;
79    }
80}
81
82// Fallback for other architectures to ensure CpuFeatures is always defined.
83#[cfg(not(any(target_arch = "x86_64", target_arch = "aarch64")))]
84bitflags! {
85    /// Represents CPU features. On unsupported architectures, this will be empty.
86    #[derive(Default, Debug, Clone, Copy, PartialEq, Eq, Hash)]
87    #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
88    #[cfg_attr(feature = "serde", serde(transparent))]
89    pub struct CpuFeatures: u32 {
90        // No features defined for this architecture by default.
91    }
92}
gdt_cpus/cpu/features.rs

gdt_cpus/cpu/
features.rs
