gdt_cpus/cpu/
cache_info.rs

1use super::{CacheLevel, CacheType};
2
3/// Represents detailed information about a specific CPU cache.
4///
5/// This structure provides insights into the cache's characteristics,
6/// such as its level in the memory hierarchy, its designated type
7/// (e.g., for data or instructions), its total size, and the size
8/// of its cache lines. This information is crucial for performance-sensitive
9/// applications that need to optimize memory access patterns.
10#[derive(Debug, Clone, Copy)]
11#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
12pub struct CacheInfo {
13    /// The hierarchical level of the cache (e.g., L1, L2, L3).
14    ///
15    /// Lower levels (like L1) are smaller, faster, and closer to the CPU core,
16    /// while higher levels (like L3) are larger, slower, and typically shared
17    /// among multiple cores.
18    pub level: CacheLevel,
19    /// The designated purpose of the cache.
20    ///
21    /// This can be:
22    /// - `Data`: Cache dedicated to storing data.
23    /// - `Instruction`: Cache dedicated to storing executable instructions.
24    /// - `Unified`: Cache used for both data and instructions.
25    pub cache_type: CacheType,
26    /// The total size of the cache, expressed in bytes.
27    ///
28    /// For example, a value of `32768` would represent a 32KB cache.
29    pub size_bytes: u64,
30    /// The size of a single cache line (also known as a cache block), in bytes.
31    ///
32    /// Data is transferred between the cache and main memory in units of cache lines.
33    /// Knowing the line size can be important for optimizing data layout to avoid
34    /// issues like false sharing in multi-threaded applications.
35    pub line_size_bytes: usize,
36}
gdt_cpus/cpu/cache_info.rs

gdt_cpus/cpu/
cache_info.rs
