gdt_cpus/cpu/
l2_domain.rs

1use crate::AffinityMask;
2
3/// A set of cores sharing one L2 cache instance.
4///
5/// Where an [`L3Domain`](crate::L3Domain) is the last-level-cache sharing group (a CCD on chiplet AMD,
6/// a cluster on hybrid Intel), an L2 domain is the much finer group that shares one L2: on most desktop
7/// parts that is a single physical core plus its SMT siblings; on hybrid Intel the efficiency cores
8/// share an L2 in clusters. Sharing L2 is the shortest core-to-core path, so this is the granularity at
9/// which two threads are "closest" - the unit for slicing a few cooperating threads out of a larger L3
10/// domain.
11///
12/// Domains are content-keyed during detection (by the lowest member LP of the cache's shared set), and
13/// each carries its own [`size_bytes`](Self::size_bytes), so heterogeneous L2 sizes (mixed core kinds)
14/// are represented exactly rather than collapsed to a per-kind average.
15#[derive(Debug, Clone)]
16#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
17pub struct L2Domain {
18    /// Size of this L2 instance in bytes.
19    pub size_bytes: u64,
20    /// The LPs (OS ids) sharing this L2 instance.
21    pub mask: AffinityMask,
22    /// Physical cores in this domain (SMT siblings counted once).
23    pub core_count: u16,
24    /// Index of the parent [`L3Domain`](crate::L3Domain) these cores share, or
25    /// [`Lp::NO_L3`](crate::Lp::NO_L3) when the machine reports no L3 (e.g. Apple Silicon). Every LP in
26    /// an L2 domain shares one L3, so this lets a caller walk the L2 groups inside a single L3 domain
27    /// without intersecting masks.
28    pub l3_domain: u8,
29}
gdt_cpus/cpu/l2_domain.rs

gdt_cpus/cpu/
l2_domain.rs
