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use nb;
pub use crate::hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use crate::pac::{spi0, SPI0, SPI1};
use crate::gpio::gpioa::{PA5, PA6, PA7};
use crate::gpio::gpiob::{PB13, PB14, PB15, PB3, PB4, PB5};
use crate::gpio::{Alternate, Floating, Input, PushPull};
use crate::rcu::{Enable, Reset, Clocks};
use crate::time::Hertz;
use crate::afio::Remap;
use core::ops::Deref;
#[derive(Debug)]
pub enum Error {
Overrun,
ModeFault,
Crc,
#[doc(hidden)]
_Extensible,
}
#[doc(hidden)]
pub trait SpiX: Deref<Target = spi0::RegisterBlock> {}
impl SpiX for SPI0 {}
impl SpiX for SPI1 {}
pub trait Pins<SPI> {
const REMAP: bool;
}
impl Pins<SPI0>
for (
PA5<Alternate<PushPull>>,
PA6<Input<Floating>>,
PA7<Alternate<PushPull>>,
)
{
const REMAP: bool = false;
}
impl Pins<SPI0>
for (
PB3<Alternate<PushPull>>,
PB4<Input<Floating>>,
PB5<Alternate<PushPull>>,
)
{
const REMAP: bool = true;
}
impl Pins<SPI1>
for (
PB13<Alternate<PushPull>>,
PB14<Input<Floating>>,
PB15<Alternate<PushPull>>,
)
{
const REMAP: bool = false;
}
pub struct Spi<SPI, PINS> {
spi: SPI,
pins: PINS,
}
impl<PINS: Pins<SPI0>> Spi<SPI0, PINS> {
pub fn spi0(
spi: SPI0,
pins: PINS,
mode: Mode,
freq: impl Into<Hertz>,
clocks: &Clocks
) -> Self
{
SPI0::remap(PINS::REMAP);
Spi::new(spi, pins, mode, freq, clocks)
}
}
impl<PINS: Pins<SPI1>> Spi<SPI1, PINS> {
pub fn spi1(
spi: SPI1,
pins: PINS,
mode: Mode,
freq: impl Into<Hertz>,
clocks: &Clocks
) -> Self
{
Spi::new(spi, pins, mode, freq, clocks)
}
}
impl<SPI, PINS> Spi<SPI, PINS> where SPI: SpiX
{
fn new(
spi: SPI,
pins: PINS,
mode: Mode,
freq: impl Into<Hertz>,
clocks: &Clocks
) -> Self where SPI: Enable + Reset {
SPI::enable();
SPI::reset();
spi.ctl1.write(|w| w.nssdrv().clear_bit());
let br = match clocks.pclk2().0 / freq.into().0 {
0 => unreachable!(),
1..=2 => 0b000,
3..=5 => 0b001,
6..=11 => 0b010,
12..=23 => 0b011,
24..=47 => 0b100,
48..=95 => 0b101,
96..=191 => 0b110,
_ => 0b111,
};
spi.ctl0.write(|w| unsafe { w
.ckph().bit(mode.phase == Phase::CaptureOnSecondTransition)
.ckpl().bit(mode.polarity == Polarity::IdleHigh)
.mstmod().set_bit()
.psc().bits(br)
.lf().clear_bit()
.swnss().set_bit()
.swnssen().set_bit()
.ro().clear_bit()
.ff16().clear_bit()
.bden().clear_bit()
.spien().set_bit()
});
Spi { spi, pins }
}
pub fn free(self) -> (SPI, PINS) {
(self.spi, self.pins)
}
}
impl<SPI: SpiX, PINS> crate::hal::spi::FullDuplex<u8> for Spi<SPI, PINS> {
type Error = Error;
fn read(&mut self) -> nb::Result<u8, Error> {
let sr = self.spi.stat.read();
Err(if sr.rxorerr().bit_is_set() {
nb::Error::Other(Error::Overrun)
} else if sr.conferr().bit_is_set() {
nb::Error::Other(Error::ModeFault)
} else if sr.crcerr().bit_is_set() {
nb::Error::Other(Error::Crc)
} else if sr.rbne().bit_is_set() {
let byte = (self.spi.data.read().bits() & 0xff) as u8;
return Ok(byte);
} else {
nb::Error::WouldBlock
})
}
fn send(&mut self, byte: u8) -> nb::Result<(), Error> {
let sr = self.spi.stat.read();
Err(if sr.rxorerr().bit_is_set() {
nb::Error::Other(Error::Overrun)
} else if sr.conferr().bit_is_set() {
nb::Error::Other(Error::ModeFault)
} else if sr.crcerr().bit_is_set() {
nb::Error::Other(Error::Crc)
} else if sr.tbe().bit_is_set() {
self.spi.data.write(|w| unsafe { w.bits(byte as u16) });
return Ok(());
} else {
nb::Error::WouldBlock
})
}
}
impl<SPI: SpiX, PINS> crate::hal::blocking::spi::transfer::Default<u8> for Spi<SPI, PINS> {}
impl<SPI: SpiX, PINS> crate::hal::blocking::spi::write::Default<u8> for Spi<SPI, PINS> {}