Module gd32vf103_pac::timer0::chctl2
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Channel control register 2
Structs
- Channel control register 2
- Register
CHCTL2
reader - Register
CHCTL2
writer
Type Definitions
- Field
CH0EN
reader - Channel 0 capture/compare function enable - Field
CH0EN
writer - Channel 0 capture/compare function enable - Field
CH0NEN
reader - Channel 0 complementary output enable - Field
CH0NEN
writer - Channel 0 complementary output enable - Field
CH0NP
reader - Channel 0 complementary output polarity - Field
CH0NP
writer - Channel 0 complementary output polarity - Field
CH0P
reader - Channel 0 capture/compare function polarity - Field
CH0P
writer - Channel 0 capture/compare function polarity - Field
CH1EN
reader - Channel 1 capture/compare function enable - Field
CH1EN
writer - Channel 1 capture/compare function enable - Field
CH1NEN
reader - Channel 1 complementary output enable - Field
CH1NEN
writer - Channel 1 complementary output enable - Field
CH1NP
reader - Channel 1 complementary output polarity - Field
CH1NP
writer - Channel 1 complementary output polarity - Field
CH1P
reader - Channel 1 capture/compare function polarity - Field
CH1P
writer - Channel 1 capture/compare function polarity - Field
CH2EN
reader - Channel 2 capture/compare function enable - Field
CH2EN
writer - Channel 2 capture/compare function enable - Field
CH2NEN
reader - Channel 2 complementary output enable - Field
CH2NEN
writer - Channel 2 complementary output enable - Field
CH2NP
reader - Channel 2 complementary output polarity - Field
CH2NP
writer - Channel 2 complementary output polarity - Field
CH2P
reader - Channel 2 capture/compare function polarity - Field
CH2P
writer - Channel 2 capture/compare function polarity - Field
CH3EN
reader - Channel 3 capture/compare function enable - Field
CH3EN
writer - Channel 3 capture/compare function enable - Field
CH3P
reader - Channel 3 capture/compare function polarity - Field
CH3P
writer - Channel 3 capture/compare function polarity