Module gd32vf103_pac::timer0::chctl0_output
source · Expand description
Channel control register 0 (output mode)
Structs
- Channel control register 0 (output mode)
- Register
CHCTL0_Output
reader - Register
CHCTL0_Output
writer
Type Definitions
- Field
CH0COMCEN
reader - Channel 0 output compare clear enable - Field
CH0COMCEN
writer - Channel 0 output compare clear enable - Field
CH0COMCTL
reader - Channel 0 compare output control - Field
CH0COMCTL
writer - Channel 0 compare output control - Field
CH0COMFEN
reader - Channel 0 output compare fast enable - Field
CH0COMFEN
writer - Channel 0 output compare fast enable - Field
CH0COMSEN
reader - Channel 0 compare output shadow enable - Field
CH0COMSEN
writer - Channel 0 compare output shadow enable - Field
CH0MS
reader - Channel 0 I/O mode selection - Field
CH0MS
writer - Channel 0 I/O mode selection - Field
CH1COMCEN
reader - Channel 1 output compare clear enable - Field
CH1COMCEN
writer - Channel 1 output compare clear enable - Field
CH1COMCTL
reader - Channel 1 compare output control - Field
CH1COMCTL
writer - Channel 1 compare output control - Field
CH1COMFEN
reader - Channel 1 output compare fast enable - Field
CH1COMFEN
writer - Channel 1 output compare fast enable - Field
CH1COMSEN
reader - Channel 1 output compare shadow enable - Field
CH1COMSEN
writer - Channel 1 output compare shadow enable - Field
CH1MS
reader - Channel 1 mode selection - Field
CH1MS
writer - Channel 1 mode selection