gd32vf103_pac/timer0/
chctl1_input.rs

1#[doc = "Register `CHCTL1_Input` reader"]
2pub struct R(crate::R<CHCTL1_INPUT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CHCTL1_INPUT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CHCTL1_INPUT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CHCTL1_INPUT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CHCTL1_Input` writer"]
17pub struct W(crate::W<CHCTL1_INPUT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CHCTL1_INPUT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CHCTL1_INPUT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CHCTL1_INPUT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CH2MS` reader - Channel 2 mode selection"]
38pub type CH2MS_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `CH2MS` writer - Channel 2 mode selection"]
40pub type CH2MS_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CHCTL1_INPUT_SPEC, u8, u8, 2, O>;
41#[doc = "Field `CH2CAPPSC` reader - Channel 2 input capture prescaler"]
42pub type CH2CAPPSC_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `CH2CAPPSC` writer - Channel 2 input capture prescaler"]
44pub type CH2CAPPSC_W<'a, const O: u8> =
45    crate::FieldWriter<'a, u16, CHCTL1_INPUT_SPEC, u8, u8, 2, O>;
46#[doc = "Field `CH2CAPFLT` reader - Channel 2 input capture filter control"]
47pub type CH2CAPFLT_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `CH2CAPFLT` writer - Channel 2 input capture filter control"]
49pub type CH2CAPFLT_W<'a, const O: u8> =
50    crate::FieldWriter<'a, u16, CHCTL1_INPUT_SPEC, u8, u8, 4, O>;
51#[doc = "Field `CH3MS` reader - Channel 3 mode selection"]
52pub type CH3MS_R = crate::FieldReader<u8, u8>;
53#[doc = "Field `CH3MS` writer - Channel 3 mode selection"]
54pub type CH3MS_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CHCTL1_INPUT_SPEC, u8, u8, 2, O>;
55#[doc = "Field `CH3CAPPSC` reader - Channel 3 input capture prescaler"]
56pub type CH3CAPPSC_R = crate::FieldReader<u8, u8>;
57#[doc = "Field `CH3CAPPSC` writer - Channel 3 input capture prescaler"]
58pub type CH3CAPPSC_W<'a, const O: u8> =
59    crate::FieldWriter<'a, u16, CHCTL1_INPUT_SPEC, u8, u8, 2, O>;
60#[doc = "Field `CH3CAPFLT` reader - Channel 3 input capture filter control"]
61pub type CH3CAPFLT_R = crate::FieldReader<u8, u8>;
62#[doc = "Field `CH3CAPFLT` writer - Channel 3 input capture filter control"]
63pub type CH3CAPFLT_W<'a, const O: u8> =
64    crate::FieldWriter<'a, u16, CHCTL1_INPUT_SPEC, u8, u8, 4, O>;
65impl R {
66    #[doc = "Bits 0:1 - Channel 2 mode selection"]
67    #[inline(always)]
68    pub fn ch2ms(&self) -> CH2MS_R {
69        CH2MS_R::new((self.bits & 3) as u8)
70    }
71    #[doc = "Bits 2:3 - Channel 2 input capture prescaler"]
72    #[inline(always)]
73    pub fn ch2cappsc(&self) -> CH2CAPPSC_R {
74        CH2CAPPSC_R::new(((self.bits >> 2) & 3) as u8)
75    }
76    #[doc = "Bits 4:7 - Channel 2 input capture filter control"]
77    #[inline(always)]
78    pub fn ch2capflt(&self) -> CH2CAPFLT_R {
79        CH2CAPFLT_R::new(((self.bits >> 4) & 0x0f) as u8)
80    }
81    #[doc = "Bits 8:9 - Channel 3 mode selection"]
82    #[inline(always)]
83    pub fn ch3ms(&self) -> CH3MS_R {
84        CH3MS_R::new(((self.bits >> 8) & 3) as u8)
85    }
86    #[doc = "Bits 10:11 - Channel 3 input capture prescaler"]
87    #[inline(always)]
88    pub fn ch3cappsc(&self) -> CH3CAPPSC_R {
89        CH3CAPPSC_R::new(((self.bits >> 10) & 3) as u8)
90    }
91    #[doc = "Bits 12:15 - Channel 3 input capture filter control"]
92    #[inline(always)]
93    pub fn ch3capflt(&self) -> CH3CAPFLT_R {
94        CH3CAPFLT_R::new(((self.bits >> 12) & 0x0f) as u8)
95    }
96}
97impl W {
98    #[doc = "Bits 0:1 - Channel 2 mode selection"]
99    #[inline(always)]
100    #[must_use]
101    pub fn ch2ms(&mut self) -> CH2MS_W<0> {
102        CH2MS_W::new(self)
103    }
104    #[doc = "Bits 2:3 - Channel 2 input capture prescaler"]
105    #[inline(always)]
106    #[must_use]
107    pub fn ch2cappsc(&mut self) -> CH2CAPPSC_W<2> {
108        CH2CAPPSC_W::new(self)
109    }
110    #[doc = "Bits 4:7 - Channel 2 input capture filter control"]
111    #[inline(always)]
112    #[must_use]
113    pub fn ch2capflt(&mut self) -> CH2CAPFLT_W<4> {
114        CH2CAPFLT_W::new(self)
115    }
116    #[doc = "Bits 8:9 - Channel 3 mode selection"]
117    #[inline(always)]
118    #[must_use]
119    pub fn ch3ms(&mut self) -> CH3MS_W<8> {
120        CH3MS_W::new(self)
121    }
122    #[doc = "Bits 10:11 - Channel 3 input capture prescaler"]
123    #[inline(always)]
124    #[must_use]
125    pub fn ch3cappsc(&mut self) -> CH3CAPPSC_W<10> {
126        CH3CAPPSC_W::new(self)
127    }
128    #[doc = "Bits 12:15 - Channel 3 input capture filter control"]
129    #[inline(always)]
130    #[must_use]
131    pub fn ch3capflt(&mut self) -> CH3CAPFLT_W<12> {
132        CH3CAPFLT_W::new(self)
133    }
134    #[doc = "Writes raw bits to the register."]
135    #[inline(always)]
136    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
137        self.0.bits(bits);
138        self
139    }
140}
141#[doc = "Channel control register 1 (input mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctl1_input](index.html) module"]
142pub struct CHCTL1_INPUT_SPEC;
143impl crate::RegisterSpec for CHCTL1_INPUT_SPEC {
144    type Ux = u16;
145}
146#[doc = "`read()` method returns [chctl1_input::R](R) reader structure"]
147impl crate::Readable for CHCTL1_INPUT_SPEC {
148    type Reader = R;
149}
150#[doc = "`write(|w| ..)` method takes [chctl1_input::W](W) writer structure"]
151impl crate::Writable for CHCTL1_INPUT_SPEC {
152    type Writer = W;
153    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
154    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
155}
156#[doc = "`reset()` method sets CHCTL1_Input to value 0"]
157impl crate::Resettable for CHCTL1_INPUT_SPEC {
158    const RESET_VALUE: Self::Ux = 0;
159}
gd32vf103_pac/timer0/chctl1_input.rs

gd32vf103_pac/timer0/
chctl1_input.rs
