gd32vf103_pac/usbfs_host/
hch7ctl.rs

1#[doc = "Register `HCH7CTL` reader"]
2pub struct R(crate::R<HCH7CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HCH7CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HCH7CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HCH7CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HCH7CTL` writer"]
17pub struct W(crate::W<HCH7CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HCH7CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HCH7CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HCH7CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MPL` reader - Maximum packet size"]
38pub type MPL_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `MPL` writer - Maximum packet size"]
40pub type MPL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCH7CTL_SPEC, u16, u16, 11, O>;
41#[doc = "Field `EPNUM` reader - Endpoint number"]
42pub type EPNUM_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `EPNUM` writer - Endpoint number"]
44pub type EPNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCH7CTL_SPEC, u8, u8, 4, O>;
45#[doc = "Field `EPDIR` reader - Endpoint direction"]
46pub type EPDIR_R = crate::BitReader<bool>;
47#[doc = "Field `EPDIR` writer - Endpoint direction"]
48pub type EPDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCH7CTL_SPEC, bool, O>;
49#[doc = "Field `LSD` reader - Low-speed device"]
50pub type LSD_R = crate::BitReader<bool>;
51#[doc = "Field `LSD` writer - Low-speed device"]
52pub type LSD_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCH7CTL_SPEC, bool, O>;
53#[doc = "Field `EPTYPE` reader - Endpoint type"]
54pub type EPTYPE_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `EPTYPE` writer - Endpoint type"]
56pub type EPTYPE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCH7CTL_SPEC, u8, u8, 2, O>;
57#[doc = "Field `DAR` reader - Device address"]
58pub type DAR_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `DAR` writer - Device address"]
60pub type DAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCH7CTL_SPEC, u8, u8, 7, O>;
61#[doc = "Field `ODDFRM` reader - Odd frame"]
62pub type ODDFRM_R = crate::BitReader<bool>;
63#[doc = "Field `ODDFRM` writer - Odd frame"]
64pub type ODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCH7CTL_SPEC, bool, O>;
65#[doc = "Field `CDIS` reader - Channel disable"]
66pub type CDIS_R = crate::BitReader<bool>;
67#[doc = "Field `CDIS` writer - Channel disable"]
68pub type CDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCH7CTL_SPEC, bool, O>;
69#[doc = "Field `CEN` reader - Channel enable"]
70pub type CEN_R = crate::BitReader<bool>;
71#[doc = "Field `CEN` writer - Channel enable"]
72pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCH7CTL_SPEC, bool, O>;
73impl R {
74    #[doc = "Bits 0:10 - Maximum packet size"]
75    #[inline(always)]
76    pub fn mpl(&self) -> MPL_R {
77        MPL_R::new((self.bits & 0x07ff) as u16)
78    }
79    #[doc = "Bits 11:14 - Endpoint number"]
80    #[inline(always)]
81    pub fn epnum(&self) -> EPNUM_R {
82        EPNUM_R::new(((self.bits >> 11) & 0x0f) as u8)
83    }
84    #[doc = "Bit 15 - Endpoint direction"]
85    #[inline(always)]
86    pub fn epdir(&self) -> EPDIR_R {
87        EPDIR_R::new(((self.bits >> 15) & 1) != 0)
88    }
89    #[doc = "Bit 17 - Low-speed device"]
90    #[inline(always)]
91    pub fn lsd(&self) -> LSD_R {
92        LSD_R::new(((self.bits >> 17) & 1) != 0)
93    }
94    #[doc = "Bits 18:19 - Endpoint type"]
95    #[inline(always)]
96    pub fn eptype(&self) -> EPTYPE_R {
97        EPTYPE_R::new(((self.bits >> 18) & 3) as u8)
98    }
99    #[doc = "Bits 22:28 - Device address"]
100    #[inline(always)]
101    pub fn dar(&self) -> DAR_R {
102        DAR_R::new(((self.bits >> 22) & 0x7f) as u8)
103    }
104    #[doc = "Bit 29 - Odd frame"]
105    #[inline(always)]
106    pub fn oddfrm(&self) -> ODDFRM_R {
107        ODDFRM_R::new(((self.bits >> 29) & 1) != 0)
108    }
109    #[doc = "Bit 30 - Channel disable"]
110    #[inline(always)]
111    pub fn cdis(&self) -> CDIS_R {
112        CDIS_R::new(((self.bits >> 30) & 1) != 0)
113    }
114    #[doc = "Bit 31 - Channel enable"]
115    #[inline(always)]
116    pub fn cen(&self) -> CEN_R {
117        CEN_R::new(((self.bits >> 31) & 1) != 0)
118    }
119}
120impl W {
121    #[doc = "Bits 0:10 - Maximum packet size"]
122    #[inline(always)]
123    #[must_use]
124    pub fn mpl(&mut self) -> MPL_W<0> {
125        MPL_W::new(self)
126    }
127    #[doc = "Bits 11:14 - Endpoint number"]
128    #[inline(always)]
129    #[must_use]
130    pub fn epnum(&mut self) -> EPNUM_W<11> {
131        EPNUM_W::new(self)
132    }
133    #[doc = "Bit 15 - Endpoint direction"]
134    #[inline(always)]
135    #[must_use]
136    pub fn epdir(&mut self) -> EPDIR_W<15> {
137        EPDIR_W::new(self)
138    }
139    #[doc = "Bit 17 - Low-speed device"]
140    #[inline(always)]
141    #[must_use]
142    pub fn lsd(&mut self) -> LSD_W<17> {
143        LSD_W::new(self)
144    }
145    #[doc = "Bits 18:19 - Endpoint type"]
146    #[inline(always)]
147    #[must_use]
148    pub fn eptype(&mut self) -> EPTYPE_W<18> {
149        EPTYPE_W::new(self)
150    }
151    #[doc = "Bits 22:28 - Device address"]
152    #[inline(always)]
153    #[must_use]
154    pub fn dar(&mut self) -> DAR_W<22> {
155        DAR_W::new(self)
156    }
157    #[doc = "Bit 29 - Odd frame"]
158    #[inline(always)]
159    #[must_use]
160    pub fn oddfrm(&mut self) -> ODDFRM_W<29> {
161        ODDFRM_W::new(self)
162    }
163    #[doc = "Bit 30 - Channel disable"]
164    #[inline(always)]
165    #[must_use]
166    pub fn cdis(&mut self) -> CDIS_W<30> {
167        CDIS_W::new(self)
168    }
169    #[doc = "Bit 31 - Channel enable"]
170    #[inline(always)]
171    #[must_use]
172    pub fn cen(&mut self) -> CEN_W<31> {
173        CEN_W::new(self)
174    }
175    #[doc = "Writes raw bits to the register."]
176    #[inline(always)]
177    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
178        self.0.bits(bits);
179        self
180    }
181}
182#[doc = "host channel-7 characteristics register (HCH7CTL)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hch7ctl](index.html) module"]
183pub struct HCH7CTL_SPEC;
184impl crate::RegisterSpec for HCH7CTL_SPEC {
185    type Ux = u32;
186}
187#[doc = "`read()` method returns [hch7ctl::R](R) reader structure"]
188impl crate::Readable for HCH7CTL_SPEC {
189    type Reader = R;
190}
191#[doc = "`write(|w| ..)` method takes [hch7ctl::W](W) writer structure"]
192impl crate::Writable for HCH7CTL_SPEC {
193    type Writer = W;
194    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
195    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
196}
197#[doc = "`reset()` method sets HCH7CTL to value 0"]
198impl crate::Resettable for HCH7CTL_SPEC {
199    const RESET_VALUE: Self::Ux = 0;
200}
gd32vf103_pac/usbfs_host/hch7ctl.rs

gd32vf103_pac/usbfs_host/
hch7ctl.rs
