gd32vf103_pac/timer5/
ctl0.rs

1#[doc = "Register `CTL0` reader"]
2pub struct R(crate::R<CTL0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTL0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTL0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTL0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTL0` writer"]
17pub struct W(crate::W<CTL0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTL0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTL0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTL0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CEN` reader - Counter enable"]
38pub type CEN_R = crate::BitReader<bool>;
39#[doc = "Field `CEN` writer - Counter enable"]
40pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
41#[doc = "Field `UPDIS` reader - Update disable"]
42pub type UPDIS_R = crate::BitReader<bool>;
43#[doc = "Field `UPDIS` writer - Update disable"]
44pub type UPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
45#[doc = "Field `UPS` reader - Update source"]
46pub type UPS_R = crate::BitReader<bool>;
47#[doc = "Field `UPS` writer - Update source"]
48pub type UPS_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
49#[doc = "Field `SPM` reader - Single pulse mode"]
50pub type SPM_R = crate::BitReader<bool>;
51#[doc = "Field `SPM` writer - Single pulse mode"]
52pub type SPM_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
53#[doc = "Field `ARSE` reader - Auto-reload shadow enable"]
54pub type ARSE_R = crate::BitReader<bool>;
55#[doc = "Field `ARSE` writer - Auto-reload shadow enable"]
56pub type ARSE_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
57impl R {
58    #[doc = "Bit 0 - Counter enable"]
59    #[inline(always)]
60    pub fn cen(&self) -> CEN_R {
61        CEN_R::new((self.bits & 1) != 0)
62    }
63    #[doc = "Bit 1 - Update disable"]
64    #[inline(always)]
65    pub fn updis(&self) -> UPDIS_R {
66        UPDIS_R::new(((self.bits >> 1) & 1) != 0)
67    }
68    #[doc = "Bit 2 - Update source"]
69    #[inline(always)]
70    pub fn ups(&self) -> UPS_R {
71        UPS_R::new(((self.bits >> 2) & 1) != 0)
72    }
73    #[doc = "Bit 3 - Single pulse mode"]
74    #[inline(always)]
75    pub fn spm(&self) -> SPM_R {
76        SPM_R::new(((self.bits >> 3) & 1) != 0)
77    }
78    #[doc = "Bit 7 - Auto-reload shadow enable"]
79    #[inline(always)]
80    pub fn arse(&self) -> ARSE_R {
81        ARSE_R::new(((self.bits >> 7) & 1) != 0)
82    }
83}
84impl W {
85    #[doc = "Bit 0 - Counter enable"]
86    #[inline(always)]
87    #[must_use]
88    pub fn cen(&mut self) -> CEN_W<0> {
89        CEN_W::new(self)
90    }
91    #[doc = "Bit 1 - Update disable"]
92    #[inline(always)]
93    #[must_use]
94    pub fn updis(&mut self) -> UPDIS_W<1> {
95        UPDIS_W::new(self)
96    }
97    #[doc = "Bit 2 - Update source"]
98    #[inline(always)]
99    #[must_use]
100    pub fn ups(&mut self) -> UPS_W<2> {
101        UPS_W::new(self)
102    }
103    #[doc = "Bit 3 - Single pulse mode"]
104    #[inline(always)]
105    #[must_use]
106    pub fn spm(&mut self) -> SPM_W<3> {
107        SPM_W::new(self)
108    }
109    #[doc = "Bit 7 - Auto-reload shadow enable"]
110    #[inline(always)]
111    #[must_use]
112    pub fn arse(&mut self) -> ARSE_W<7> {
113        ARSE_W::new(self)
114    }
115    #[doc = "Writes raw bits to the register."]
116    #[inline(always)]
117    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
118        self.0.bits(bits);
119        self
120    }
121}
122#[doc = "control register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl0](index.html) module"]
123pub struct CTL0_SPEC;
124impl crate::RegisterSpec for CTL0_SPEC {
125    type Ux = u16;
126}
127#[doc = "`read()` method returns [ctl0::R](R) reader structure"]
128impl crate::Readable for CTL0_SPEC {
129    type Reader = R;
130}
131#[doc = "`write(|w| ..)` method takes [ctl0::W](W) writer structure"]
132impl crate::Writable for CTL0_SPEC {
133    type Writer = W;
134    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
135    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
136}
137#[doc = "`reset()` method sets CTL0 to value 0"]
138impl crate::Resettable for CTL0_SPEC {
139    const RESET_VALUE: Self::Ux = 0;
140}
gd32vf103_pac/timer5/ctl0.rs

gd32vf103_pac/timer5/
ctl0.rs
