gd32vf103_pac/spi0/
ctl0.rs

1#[doc = "Register `CTL0` reader"]
2pub struct R(crate::R<CTL0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTL0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTL0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTL0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTL0` writer"]
17pub struct W(crate::W<CTL0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTL0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTL0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTL0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CKPH` reader - Clock Phase Selection"]
38pub type CKPH_R = crate::BitReader<bool>;
39#[doc = "Field `CKPH` writer - Clock Phase Selection"]
40pub type CKPH_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
41#[doc = "Field `CKPL` reader - Clock polarity Selection"]
42pub type CKPL_R = crate::BitReader<bool>;
43#[doc = "Field `CKPL` writer - Clock polarity Selection"]
44pub type CKPL_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
45#[doc = "Field `MSTMOD` reader - Master Mode Enable"]
46pub type MSTMOD_R = crate::BitReader<bool>;
47#[doc = "Field `MSTMOD` writer - Master Mode Enable"]
48pub type MSTMOD_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
49#[doc = "Field `PSC` reader - Master Clock Prescaler Selection"]
50pub type PSC_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `PSC` writer - Master Clock Prescaler Selection"]
52pub type PSC_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CTL0_SPEC, u8, u8, 3, O>;
53#[doc = "Field `SPIEN` reader - SPI enable"]
54pub type SPIEN_R = crate::BitReader<bool>;
55#[doc = "Field `SPIEN` writer - SPI enable"]
56pub type SPIEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
57#[doc = "Field `LF` reader - LSB First Mode"]
58pub type LF_R = crate::BitReader<bool>;
59#[doc = "Field `LF` writer - LSB First Mode"]
60pub type LF_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
61#[doc = "Field `SWNSS` reader - NSS Pin Selection In NSS Software Mode"]
62pub type SWNSS_R = crate::BitReader<bool>;
63#[doc = "Field `SWNSS` writer - NSS Pin Selection In NSS Software Mode"]
64pub type SWNSS_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
65#[doc = "Field `SWNSSEN` reader - NSS Software Mode Selection"]
66pub type SWNSSEN_R = crate::BitReader<bool>;
67#[doc = "Field `SWNSSEN` writer - NSS Software Mode Selection"]
68pub type SWNSSEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
69#[doc = "Field `RO` reader - Receive only"]
70pub type RO_R = crate::BitReader<bool>;
71#[doc = "Field `RO` writer - Receive only"]
72pub type RO_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
73#[doc = "Field `FF16` reader - Data frame format"]
74pub type FF16_R = crate::BitReader<bool>;
75#[doc = "Field `FF16` writer - Data frame format"]
76pub type FF16_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
77#[doc = "Field `CRCNT` reader - CRC Next Transfer"]
78pub type CRCNT_R = crate::BitReader<bool>;
79#[doc = "Field `CRCNT` writer - CRC Next Transfer"]
80pub type CRCNT_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
81#[doc = "Field `CRCEN` reader - CRC Calculation Enable"]
82pub type CRCEN_R = crate::BitReader<bool>;
83#[doc = "Field `CRCEN` writer - CRC Calculation Enable"]
84pub type CRCEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
85#[doc = "Field `BDOEN` reader - Bidirectional Transmit output enable"]
86pub type BDOEN_R = crate::BitReader<bool>;
87#[doc = "Field `BDOEN` writer - Bidirectional Transmit output enable"]
88pub type BDOEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
89#[doc = "Field `BDEN` reader - Bidirectional enable"]
90pub type BDEN_R = crate::BitReader<bool>;
91#[doc = "Field `BDEN` writer - Bidirectional enable"]
92pub type BDEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTL0_SPEC, bool, O>;
93impl R {
94    #[doc = "Bit 0 - Clock Phase Selection"]
95    #[inline(always)]
96    pub fn ckph(&self) -> CKPH_R {
97        CKPH_R::new((self.bits & 1) != 0)
98    }
99    #[doc = "Bit 1 - Clock polarity Selection"]
100    #[inline(always)]
101    pub fn ckpl(&self) -> CKPL_R {
102        CKPL_R::new(((self.bits >> 1) & 1) != 0)
103    }
104    #[doc = "Bit 2 - Master Mode Enable"]
105    #[inline(always)]
106    pub fn mstmod(&self) -> MSTMOD_R {
107        MSTMOD_R::new(((self.bits >> 2) & 1) != 0)
108    }
109    #[doc = "Bits 3:5 - Master Clock Prescaler Selection"]
110    #[inline(always)]
111    pub fn psc(&self) -> PSC_R {
112        PSC_R::new(((self.bits >> 3) & 7) as u8)
113    }
114    #[doc = "Bit 6 - SPI enable"]
115    #[inline(always)]
116    pub fn spien(&self) -> SPIEN_R {
117        SPIEN_R::new(((self.bits >> 6) & 1) != 0)
118    }
119    #[doc = "Bit 7 - LSB First Mode"]
120    #[inline(always)]
121    pub fn lf(&self) -> LF_R {
122        LF_R::new(((self.bits >> 7) & 1) != 0)
123    }
124    #[doc = "Bit 8 - NSS Pin Selection In NSS Software Mode"]
125    #[inline(always)]
126    pub fn swnss(&self) -> SWNSS_R {
127        SWNSS_R::new(((self.bits >> 8) & 1) != 0)
128    }
129    #[doc = "Bit 9 - NSS Software Mode Selection"]
130    #[inline(always)]
131    pub fn swnssen(&self) -> SWNSSEN_R {
132        SWNSSEN_R::new(((self.bits >> 9) & 1) != 0)
133    }
134    #[doc = "Bit 10 - Receive only"]
135    #[inline(always)]
136    pub fn ro(&self) -> RO_R {
137        RO_R::new(((self.bits >> 10) & 1) != 0)
138    }
139    #[doc = "Bit 11 - Data frame format"]
140    #[inline(always)]
141    pub fn ff16(&self) -> FF16_R {
142        FF16_R::new(((self.bits >> 11) & 1) != 0)
143    }
144    #[doc = "Bit 12 - CRC Next Transfer"]
145    #[inline(always)]
146    pub fn crcnt(&self) -> CRCNT_R {
147        CRCNT_R::new(((self.bits >> 12) & 1) != 0)
148    }
149    #[doc = "Bit 13 - CRC Calculation Enable"]
150    #[inline(always)]
151    pub fn crcen(&self) -> CRCEN_R {
152        CRCEN_R::new(((self.bits >> 13) & 1) != 0)
153    }
154    #[doc = "Bit 14 - Bidirectional Transmit output enable"]
155    #[inline(always)]
156    pub fn bdoen(&self) -> BDOEN_R {
157        BDOEN_R::new(((self.bits >> 14) & 1) != 0)
158    }
159    #[doc = "Bit 15 - Bidirectional enable"]
160    #[inline(always)]
161    pub fn bden(&self) -> BDEN_R {
162        BDEN_R::new(((self.bits >> 15) & 1) != 0)
163    }
164}
165impl W {
166    #[doc = "Bit 0 - Clock Phase Selection"]
167    #[inline(always)]
168    #[must_use]
169    pub fn ckph(&mut self) -> CKPH_W<0> {
170        CKPH_W::new(self)
171    }
172    #[doc = "Bit 1 - Clock polarity Selection"]
173    #[inline(always)]
174    #[must_use]
175    pub fn ckpl(&mut self) -> CKPL_W<1> {
176        CKPL_W::new(self)
177    }
178    #[doc = "Bit 2 - Master Mode Enable"]
179    #[inline(always)]
180    #[must_use]
181    pub fn mstmod(&mut self) -> MSTMOD_W<2> {
182        MSTMOD_W::new(self)
183    }
184    #[doc = "Bits 3:5 - Master Clock Prescaler Selection"]
185    #[inline(always)]
186    #[must_use]
187    pub fn psc(&mut self) -> PSC_W<3> {
188        PSC_W::new(self)
189    }
190    #[doc = "Bit 6 - SPI enable"]
191    #[inline(always)]
192    #[must_use]
193    pub fn spien(&mut self) -> SPIEN_W<6> {
194        SPIEN_W::new(self)
195    }
196    #[doc = "Bit 7 - LSB First Mode"]
197    #[inline(always)]
198    #[must_use]
199    pub fn lf(&mut self) -> LF_W<7> {
200        LF_W::new(self)
201    }
202    #[doc = "Bit 8 - NSS Pin Selection In NSS Software Mode"]
203    #[inline(always)]
204    #[must_use]
205    pub fn swnss(&mut self) -> SWNSS_W<8> {
206        SWNSS_W::new(self)
207    }
208    #[doc = "Bit 9 - NSS Software Mode Selection"]
209    #[inline(always)]
210    #[must_use]
211    pub fn swnssen(&mut self) -> SWNSSEN_W<9> {
212        SWNSSEN_W::new(self)
213    }
214    #[doc = "Bit 10 - Receive only"]
215    #[inline(always)]
216    #[must_use]
217    pub fn ro(&mut self) -> RO_W<10> {
218        RO_W::new(self)
219    }
220    #[doc = "Bit 11 - Data frame format"]
221    #[inline(always)]
222    #[must_use]
223    pub fn ff16(&mut self) -> FF16_W<11> {
224        FF16_W::new(self)
225    }
226    #[doc = "Bit 12 - CRC Next Transfer"]
227    #[inline(always)]
228    #[must_use]
229    pub fn crcnt(&mut self) -> CRCNT_W<12> {
230        CRCNT_W::new(self)
231    }
232    #[doc = "Bit 13 - CRC Calculation Enable"]
233    #[inline(always)]
234    #[must_use]
235    pub fn crcen(&mut self) -> CRCEN_W<13> {
236        CRCEN_W::new(self)
237    }
238    #[doc = "Bit 14 - Bidirectional Transmit output enable"]
239    #[inline(always)]
240    #[must_use]
241    pub fn bdoen(&mut self) -> BDOEN_W<14> {
242        BDOEN_W::new(self)
243    }
244    #[doc = "Bit 15 - Bidirectional enable"]
245    #[inline(always)]
246    #[must_use]
247    pub fn bden(&mut self) -> BDEN_W<15> {
248        BDEN_W::new(self)
249    }
250    #[doc = "Writes raw bits to the register."]
251    #[inline(always)]
252    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
253        self.0.bits(bits);
254        self
255    }
256}
257#[doc = "control register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl0](index.html) module"]
258pub struct CTL0_SPEC;
259impl crate::RegisterSpec for CTL0_SPEC {
260    type Ux = u16;
261}
262#[doc = "`read()` method returns [ctl0::R](R) reader structure"]
263impl crate::Readable for CTL0_SPEC {
264    type Reader = R;
265}
266#[doc = "`write(|w| ..)` method takes [ctl0::W](W) writer structure"]
267impl crate::Writable for CTL0_SPEC {
268    type Writer = W;
269    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
270    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
271}
272#[doc = "`reset()` method sets CTL0 to value 0"]
273impl crate::Resettable for CTL0_SPEC {
274    const RESET_VALUE: Self::Ux = 0;
275}
gd32vf103_pac/spi0/ctl0.rs

gd32vf103_pac/spi0/
ctl0.rs
