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#[doc = "Reader of register CTL1"] pub type R = crate::R<u32, super::CTL1>; #[doc = "Writer for register CTL1"] pub type W = crate::W<u32, super::CTL1>; #[doc = "Register CTL1 `reset()`'s with value 0"] impl crate::ResetValue for super::CTL1 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `TSVREN`"] pub type TSVREN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSVREN`"] pub struct TSVREN_W<'a> { w: &'a mut W, } impl<'a> TSVREN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); self.w } } #[doc = "Reader of field `SWRCST`"] pub type SWRCST_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SWRCST`"] pub struct SWRCST_W<'a> { w: &'a mut W, } impl<'a> SWRCST_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); self.w } } #[doc = "Reader of field `SWICST`"] pub type SWICST_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SWICST`"] pub struct SWICST_W<'a> { w: &'a mut W, } impl<'a> SWICST_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); self.w } } #[doc = "Reader of field `ETERC`"] pub type ETERC_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ETERC`"] pub struct ETERC_W<'a> { w: &'a mut W, } impl<'a> ETERC_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); self.w } } #[doc = "Reader of field `ETSRC`"] pub type ETSRC_R = crate::R<u8, u8>; #[doc = "Write proxy for field `ETSRC`"] pub struct ETSRC_W<'a> { w: &'a mut W, } impl<'a> ETSRC_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 17)) | (((value as u32) & 0x07) << 17); self.w } } #[doc = "Reader of field `ETEIC`"] pub type ETEIC_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ETEIC`"] pub struct ETEIC_W<'a> { w: &'a mut W, } impl<'a> ETEIC_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } #[doc = "Reader of field `ETSIC`"] pub type ETSIC_R = crate::R<u8, u8>; #[doc = "Write proxy for field `ETSIC`"] pub struct ETSIC_W<'a> { w: &'a mut W, } impl<'a> ETSIC_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12); self.w } } #[doc = "Reader of field `DAL`"] pub type DAL_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DAL`"] pub struct DAL_W<'a> { w: &'a mut W, } impl<'a> DAL_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); self.w } } #[doc = "Reader of field `DMA`"] pub type DMA_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DMA`"] pub struct DMA_W<'a> { w: &'a mut W, } impl<'a> DMA_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Reader of field `RSTCLB`"] pub type RSTCLB_R = crate::R<bool, bool>; #[doc = "Write proxy for field `RSTCLB`"] pub struct RSTCLB_W<'a> { w: &'a mut W, } impl<'a> RSTCLB_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `CLB`"] pub type CLB_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CLB`"] pub struct CLB_W<'a> { w: &'a mut W, } impl<'a> CLB_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = "Reader of field `CTN`"] pub type CTN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CTN`"] pub struct CTN_W<'a> { w: &'a mut W, } impl<'a> CTN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `ADCON`"] pub type ADCON_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ADCON`"] pub struct ADCON_W<'a> { w: &'a mut W, } impl<'a> ADCON_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } impl R { #[doc = "Bit 23 - Channel 16 and 17 enable of ADC0"] #[inline(always)] pub fn tsvren(&self) -> TSVREN_R { TSVREN_R::new(((self.bits >> 23) & 0x01) != 0) } #[doc = "Bit 22 - Start on regular channel"] #[inline(always)] pub fn swrcst(&self) -> SWRCST_R { SWRCST_R::new(((self.bits >> 22) & 0x01) != 0) } #[doc = "Bit 21 - Start on inserted channel"] #[inline(always)] pub fn swicst(&self) -> SWICST_R { SWICST_R::new(((self.bits >> 21) & 0x01) != 0) } #[doc = "Bit 20 - External trigger enable for regular channel"] #[inline(always)] pub fn eterc(&self) -> ETERC_R { ETERC_R::new(((self.bits >> 20) & 0x01) != 0) } #[doc = "Bits 17:19 - External trigger select for regular channel"] #[inline(always)] pub fn etsrc(&self) -> ETSRC_R { ETSRC_R::new(((self.bits >> 17) & 0x07) as u8) } #[doc = "Bit 15 - External trigger select for inserted channel"] #[inline(always)] pub fn eteic(&self) -> ETEIC_R { ETEIC_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bits 12:14 - External trigger select for inserted channel"] #[inline(always)] pub fn etsic(&self) -> ETSIC_R { ETSIC_R::new(((self.bits >> 12) & 0x07) as u8) } #[doc = "Bit 11 - Data alignment"] #[inline(always)] pub fn dal(&self) -> DAL_R { DAL_R::new(((self.bits >> 11) & 0x01) != 0) } #[doc = "Bit 8 - DMA request enable"] #[inline(always)] pub fn dma(&self) -> DMA_R { DMA_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 3 - Reset calibration"] #[inline(always)] pub fn rstclb(&self) -> RSTCLB_R { RSTCLB_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 2 - ADC calibration"] #[inline(always)] pub fn clb(&self) -> CLB_R { CLB_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 1 - Continuous mode"] #[inline(always)] pub fn ctn(&self) -> CTN_R { CTN_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 0 - ADC on"] #[inline(always)] pub fn adcon(&self) -> ADCON_R { ADCON_R::new((self.bits & 0x01) != 0) } } impl W { #[doc = "Bit 23 - Channel 16 and 17 enable of ADC0"] #[inline(always)] pub fn tsvren(&mut self) -> TSVREN_W { TSVREN_W { w: self } } #[doc = "Bit 22 - Start on regular channel"] #[inline(always)] pub fn swrcst(&mut self) -> SWRCST_W { SWRCST_W { w: self } } #[doc = "Bit 21 - Start on inserted channel"] #[inline(always)] pub fn swicst(&mut self) -> SWICST_W { SWICST_W { w: self } } #[doc = "Bit 20 - External trigger enable for regular channel"] #[inline(always)] pub fn eterc(&mut self) -> ETERC_W { ETERC_W { w: self } } #[doc = "Bits 17:19 - External trigger select for regular channel"] #[inline(always)] pub fn etsrc(&mut self) -> ETSRC_W { ETSRC_W { w: self } } #[doc = "Bit 15 - External trigger select for inserted channel"] #[inline(always)] pub fn eteic(&mut self) -> ETEIC_W { ETEIC_W { w: self } } #[doc = "Bits 12:14 - External trigger select for inserted channel"] #[inline(always)] pub fn etsic(&mut self) -> ETSIC_W { ETSIC_W { w: self } } #[doc = "Bit 11 - Data alignment"] #[inline(always)] pub fn dal(&mut self) -> DAL_W { DAL_W { w: self } } #[doc = "Bit 8 - DMA request enable"] #[inline(always)] pub fn dma(&mut self) -> DMA_W { DMA_W { w: self } } #[doc = "Bit 3 - Reset calibration"] #[inline(always)] pub fn rstclb(&mut self) -> RSTCLB_W { RSTCLB_W { w: self } } #[doc = "Bit 2 - ADC calibration"] #[inline(always)] pub fn clb(&mut self) -> CLB_W { CLB_W { w: self } } #[doc = "Bit 1 - Continuous mode"] #[inline(always)] pub fn ctn(&mut self) -> CTN_W { CTN_W { w: self } } #[doc = "Bit 0 - ADC on"] #[inline(always)] pub fn adcon(&mut self) -> ADCON_W { ADCON_W { w: self } } }