[−][src]Struct gd32vf103_pac::dac::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub ctl: CTL,
    pub swt: SWT,
    pub dac0_r12dh: DAC0_R12DH,
    pub dac0_l12dh: DAC0_L12DH,
    pub dac0_r8dh: DAC0_R8DH,
    pub dac1_r12dh: DAC1_R12DH,
    pub dac1_l12dh: DAC1_L12DH,
    pub dac1_r8dh: DAC1_R8DH,
    pub dacc_r12dh: DACC_R12DH,
    pub dacc_l12dh: DACC_L12DH,
    pub dacc_r8dh: DACC_R8DH,
    pub dac0_do: DAC0_DO,
    pub dac1_do: DAC1_DO,
}

Register block

Fields

ctl: CTL

0x00 - control register

swt: SWT

0x04 - software trigger register

dac0_r12dh: DAC0_R12DH

0x08 - DAC0 12-bit right-aligned data holding register

dac0_l12dh: DAC0_L12DH

0x0c - DAC0 12-bit left-aligned data holding register

dac0_r8dh: DAC0_R8DH

0x10 - DAC0 8-bit right aligned data holding register

dac1_r12dh: DAC1_R12DH

0x14 - DAC1 12-bit right-aligned data holding register

dac1_l12dh: DAC1_L12DH

0x18 - DAC1 12-bit left aligned data holding register

dac1_r8dh: DAC1_R8DH

0x1c - DAC1 8-bit right aligned data holding register

dacc_r12dh: DACC_R12DH

0x20 - DAC concurrent mode 12-bit right-aligned data holding register

dacc_l12dh: DACC_L12DH

0x24 - DAC concurrent mode 12-bit left aligned data holding register

dacc_r8dh: DACC_R8DH

0x28 - DAC concurrent mode 8-bit right aligned data holding register

dac0_do: DAC0_DO

0x2c - DAC0 data output register

dac1_do: DAC1_DO

0x30 - DAC1 data output register

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