gd32f2/gd32f207/exmc/
npinten2.rs

1#[doc = "Register `NPINTEN2` reader"]
2pub type R = crate::R<Npinten2Spec>;
3#[doc = "Register `NPINTEN2` writer"]
4pub type W = crate::W<Npinten2Spec>;
5#[doc = "Field `INTRS` reader - Interrupt rising edge status"]
6pub type IntrsR = crate::BitReader;
7#[doc = "Field `INTRS` writer - Interrupt rising edge status"]
8pub type IntrsW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `INTHS` reader - Interrupt high-level status"]
10pub type InthsR = crate::BitReader;
11#[doc = "Field `INTHS` writer - Interrupt high-level status"]
12pub type InthsW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `INTFS` reader - Interrupt falling edge status"]
14pub type IntfsR = crate::BitReader;
15#[doc = "Field `INTFS` writer - Interrupt falling edge status"]
16pub type IntfsW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `INTREN` reader - Interrupt rising edge detection enable bit"]
18pub type IntrenR = crate::BitReader;
19#[doc = "Field `INTREN` writer - Interrupt rising edge detection enable bit"]
20pub type IntrenW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `INTHEN` reader - Interrupt high-level detection enable"]
22pub type InthenR = crate::BitReader;
23#[doc = "Field `INTHEN` writer - Interrupt high-level detection enable"]
24pub type InthenW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `INTFEN` reader - Interrupt falling edge detection enable"]
26pub type IntfenR = crate::BitReader;
27#[doc = "Field `INTFEN` writer - Interrupt falling edge detection enable"]
28pub type IntfenW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FFEPT` reader - FIFO empty flag"]
30pub type FfeptR = crate::BitReader;
31impl R {
32    #[doc = "Bit 0 - Interrupt rising edge status"]
33    #[inline(always)]
34    pub fn intrs(&self) -> IntrsR {
35        IntrsR::new((self.bits & 1) != 0)
36    }
37    #[doc = "Bit 1 - Interrupt high-level status"]
38    #[inline(always)]
39    pub fn inths(&self) -> InthsR {
40        InthsR::new(((self.bits >> 1) & 1) != 0)
41    }
42    #[doc = "Bit 2 - Interrupt falling edge status"]
43    #[inline(always)]
44    pub fn intfs(&self) -> IntfsR {
45        IntfsR::new(((self.bits >> 2) & 1) != 0)
46    }
47    #[doc = "Bit 3 - Interrupt rising edge detection enable bit"]
48    #[inline(always)]
49    pub fn intren(&self) -> IntrenR {
50        IntrenR::new(((self.bits >> 3) & 1) != 0)
51    }
52    #[doc = "Bit 4 - Interrupt high-level detection enable"]
53    #[inline(always)]
54    pub fn inthen(&self) -> InthenR {
55        InthenR::new(((self.bits >> 4) & 1) != 0)
56    }
57    #[doc = "Bit 5 - Interrupt falling edge detection enable"]
58    #[inline(always)]
59    pub fn intfen(&self) -> IntfenR {
60        IntfenR::new(((self.bits >> 5) & 1) != 0)
61    }
62    #[doc = "Bit 6 - FIFO empty flag"]
63    #[inline(always)]
64    pub fn ffept(&self) -> FfeptR {
65        FfeptR::new(((self.bits >> 6) & 1) != 0)
66    }
67}
68impl W {
69    #[doc = "Bit 0 - Interrupt rising edge status"]
70    #[inline(always)]
71    #[must_use]
72    pub fn intrs(&mut self) -> IntrsW<Npinten2Spec> {
73        IntrsW::new(self, 0)
74    }
75    #[doc = "Bit 1 - Interrupt high-level status"]
76    #[inline(always)]
77    #[must_use]
78    pub fn inths(&mut self) -> InthsW<Npinten2Spec> {
79        InthsW::new(self, 1)
80    }
81    #[doc = "Bit 2 - Interrupt falling edge status"]
82    #[inline(always)]
83    #[must_use]
84    pub fn intfs(&mut self) -> IntfsW<Npinten2Spec> {
85        IntfsW::new(self, 2)
86    }
87    #[doc = "Bit 3 - Interrupt rising edge detection enable bit"]
88    #[inline(always)]
89    #[must_use]
90    pub fn intren(&mut self) -> IntrenW<Npinten2Spec> {
91        IntrenW::new(self, 3)
92    }
93    #[doc = "Bit 4 - Interrupt high-level detection enable"]
94    #[inline(always)]
95    #[must_use]
96    pub fn inthen(&mut self) -> InthenW<Npinten2Spec> {
97        InthenW::new(self, 4)
98    }
99    #[doc = "Bit 5 - Interrupt falling edge detection enable"]
100    #[inline(always)]
101    #[must_use]
102    pub fn intfen(&mut self) -> IntfenW<Npinten2Spec> {
103        IntfenW::new(self, 5)
104    }
105}
106#[doc = "NAND flash/PC card interrupt enable register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`npinten2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`npinten2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct Npinten2Spec;
108impl crate::RegisterSpec for Npinten2Spec {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`npinten2::R`](R) reader structure"]
112impl crate::Readable for Npinten2Spec {}
113#[doc = "`write(|w| ..)` method takes [`npinten2::W`](W) writer structure"]
114impl crate::Writable for Npinten2Spec {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets NPINTEN2 to value 0x40"]
120impl crate::Resettable for Npinten2Spec {
121    const RESET_VALUE: u32 = 0x40;
122}
gd32f2/gd32f207/exmc/npinten2.rs

gd32f2/gd32f207/exmc/
npinten2.rs
