Struct gd32f1x0_hal::pac::timer13::RegisterBlock

source · [−]
#[repr(C)]
pub struct RegisterBlock {
    pub ctl0: Reg<CTL0_SPEC>,
    pub dmainten: Reg<DMAINTEN_SPEC>,
    pub intf: Reg<INTF_SPEC>,
    pub swevg: Reg<SWEVG_SPEC>,
    pub chctl2: Reg<CHCTL2_SPEC>,
    pub cnt: Reg<CNT_SPEC>,
    pub psc: Reg<PSC_SPEC>,
    pub car: Reg<CAR_SPEC>,
    pub ch0cv: Reg<CH0CV_SPEC>,
    pub irmp: Reg<IRMP_SPEC>,
    /* private fields */
}
Expand description

Register block

Fields

ctl0: Reg<CTL0_SPEC>

0x00 - control register 1

dmainten: Reg<DMAINTEN_SPEC>

0x0c - Interrupt enable register

intf: Reg<INTF_SPEC>

0x10 - interrupt flag register

swevg: Reg<SWEVG_SPEC>

0x14 - Software event generation register

chctl2: Reg<CHCTL2_SPEC>

0x20 - Channel control register 2

cnt: Reg<CNT_SPEC>

0x24 - Counter register

psc: Reg<PSC_SPEC>

0x28 - Prescaler register

car: Reg<CAR_SPEC>

0x2c - Counter auto reload register

ch0cv: Reg<CH0CV_SPEC>

0x34 - Channel 0 capture/compare value register

irmp: Reg<IRMP_SPEC>

0x50 - Channel input remap register

Implementations

0x18 - Channel control register 0 (input mode)

0x18 - Channel control register 0 (output mode)

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