Module gd32f1x0_hal::pac::timer14::chctl2 [−][src]
Expand description
Channel control register 2
Structs
| CH0EN_W | Field |
| CH0NEN_R | Field |
| CH0NEN_W | Field |
| CH0NP_W | Field |
| CH0P_W | Field |
| CH1EN_R | Field |
| CH1EN_W | Field |
| CH1NP_R | Field |
| CH1NP_W | Field |
| CH1P_R | Field |
| CH1P_W | Field |
| CHCTL2_SPEC | Channel control register 2 |
| R | Register |
| W | Register |
Enums
| CH0NEN_A | Channel 0 complementary output enable |
| CH1EN_A | Channel 1 polarity |
| CH1NP_A | Channel 1 complementary output polarity |
| CH1P_A | Channel 1 polarity |
Type Definitions
| CH0EN_A | Channel 0 enable |
| CH0EN_R | Field |
| CH0NP_A | Channel 0 complementary output polarity |
| CH0NP_R | Field |
| CH0P_A | Channel 0 polarity |
| CH0P_R | Field |