Module gd32f1x0_hal::pac::timer1::chctl1_input

Channel control register 1 (input mode)

Structs

CH2CAPFLT_W	Field CH2CAPFLT writer - Channel 2 input capture filter control
CH2CAPPSC_W	Field CH2CAPPSC writer - Channel 2 input capture prescaler
CH2MS_W	Field CH2MS writer - Channel 2 mode selection
CH3CAPFLT_R	Field CH3CAPFLT reader - Channel 3 input capture filter control
CH3CAPFLT_W	Field CH3CAPFLT writer - Channel 3 input capture filter control
CH3CAPPSC_R	Field CH3CAPPSC reader - Channel 3 input capture prescaler
CH3CAPPSC_W	Field CH3CAPPSC writer - Channel 3 input capture prescaler
CH3MS_R	Field CH3MS reader - Channel 3 mode selection
CH3MS_W	Field CH3MS writer - Channel 3 mode selection
CHCTL1_INPUT_SPEC	Channel control register 1 (input mode)
R	Register CHCTL1_Input reader
W	Register CHCTL1_Input writer

Enums

CH3CAPFLT_A	Channel 3 input capture filter control
CH3CAPPSC_A	Channel 3 input capture prescaler
CH3MS_A	Channel 3 mode selection

Type Definitions

CH2CAPFLT_A	Channel 2 input capture filter control
CH2CAPFLT_R	Field CH2CAPFLT reader - Channel 2 input capture filter control
CH2CAPPSC_A	Channel 2 input capture prescaler
CH2CAPPSC_R	Field CH2CAPPSC reader - Channel 2 input capture prescaler
CH2MS_A	Channel 2 mode selection
CH2MS_R	Field CH2MS reader - Channel 2 mode selection