Module gd32f1x0_hal::pac::spi0::ctl0

control register 0

Structs

BDEN_R	Field BDEN reader - Bidirectional enable
BDEN_W	Field BDEN writer - Bidirectional enable
BDOEN_R	Field BDOEN reader - Bidirectional Transmit output enable
BDOEN_W	Field BDOEN writer - Bidirectional Transmit output enable
CKPH_R	Field CKPH reader - Clock Phase Selection
CKPH_W	Field CKPH writer - Clock Phase Selection
CKPL_R	Field CKPL reader - Clock Polarity Selection
CKPL_W	Field CKPL writer - Clock Polarity Selection
CRCEN_R	Field CRCEN reader - Hardware CRC calculation enable
CRCEN_W	Field CRCEN writer - Hardware CRC calculation enable
CRCNT_R	Field CRCNT reader - CRC transfer next
CRCNT_W	Field CRCNT writer - CRC transfer next
CTL0_SPEC	control register 0
FF16_R	Field FF16 reader - Data frame format
FF16_W	Field FF16 writer - Data frame format
LF_R	Field LF reader - LSB First Mode
LF_W	Field LF writer - LSB First Mode
MSTMOD_R	Field MSTMOD reader - Master selection
MSTMOD_W	Field MSTMOD writer - Master selection
PSC_R	Field PSC reader - Master Clock Prescaler Selection
PSC_W	Field PSC writer - Master Clock Prescaler Selection
R	Register CTL0 reader
RO_R	Field RO reader - Receive only
RO_W	Field RO writer - Receive only
SPIEN_R	Field SPIEN reader - SPI enable
SPIEN_W	Field SPIEN writer - SPI enable
SWNSSEN_R	Field SWNSSEN reader - NSS Software Mode Selection
SWNSSEN_W	Field SWNSSEN writer - NSS Software Mode Selection
SWNSS_R	Field SWNSS reader - NSS Pin Selection In NSS Software Mode
SWNSS_W	Field SWNSS writer - NSS Pin Selection In NSS Software Mode
W	Register CTL0 writer

Enums

BDEN_A	Bidirectional enable
BDOEN_A	Bidirectional Transmit output enable
CKPH_A	Clock Phase Selection
CKPL_A	Clock Polarity Selection
CRCEN_A	Hardware CRC calculation enable
CRCNT_A	CRC transfer next
FF16_A	Data frame format
LF_A	LSB First Mode
MSTMOD_A	Master selection
PSC_A	Master Clock Prescaler Selection
RO_A	Receive only
SPIEN_A	SPI enable
SWNSSEN_A	NSS Software Mode Selection
SWNSS_A	NSS Pin Selection In NSS Software Mode