Module gd32f1x0_hal::pac::dma::ch3ctl0 [−][src]
Expand description
DMA channel configuration register (DMA_CH3CTL0)
Structs
CH3CTL0_SPEC | DMA channel configuration register (DMA_CH3CTL0) |
CHEN_R | Field |
CHEN_W | Field |
CMEN_R | Field |
CMEN_W | Field |
DIR_R | Field |
DIR_W | Field |
FTFIE_R | Field |
FTFIE_W | Field |
HTFIE_R | Field |
HTFIE_W | Field |
M2M_R | Field |
M2M_W | Field |
MNAGA_W | Field |
MWIDTH_W | Field |
PNAGA_R | Field |
PNAGA_W | Field |
PRIO_R | Field |
PRIO_W | Field |
PWIDTH_R | Field |
PWIDTH_W | Field |
R | Register |
TAEIE_R | Field |
TAEIE_W | Field |
W | Register |
Enums
CHEN_A | Channel enable |
CMEN_A | Circular mode enable |
DIR_A | Transfer mode |
FTFIE_A | Enable bit for full transfer finish interrupt |
HTFIE_A | Enable bit for half transfer finish interrupt |
M2M_A | Memory to memory mode |
PNAGA_A | Next address generation algorithm of peripheral |
PRIO_A | Priority Level of this channel |
PWIDTH_A | Transfer data size of peripheral |
TAEIE_A | Enable bit for tranfer access error interrupt |
Type Definitions
MNAGA_A | Next address generation algorithm of memory |
MNAGA_R | Field |
MWIDTH_A | Transfer data size of memory |
MWIDTH_R | Field |