gd32f1/gd32f190/dma/
ch5ctl.rs

1#[doc = "Register `CH5CTL` reader"]
2pub type R = crate::R<Ch5ctlSpec>;
3#[doc = "Register `CH5CTL` writer"]
4pub type W = crate::W<Ch5ctlSpec>;
5#[doc = "Channel enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Chen {
8    #[doc = "0: Channel disabled"]
9    Disabled = 0,
10    #[doc = "1: Channel enabled"]
11    Enabled = 1,
12}
13impl From<Chen> for bool {
14    #[inline(always)]
15    fn from(variant: Chen) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `CHEN` reader - Channel enable"]
20pub type ChenR = crate::BitReader<Chen>;
21impl ChenR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Chen {
25        match self.bits {
26            false => Chen::Disabled,
27            true => Chen::Enabled,
28        }
29    }
30    #[doc = "Channel disabled"]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == Chen::Disabled
34    }
35    #[doc = "Channel enabled"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == Chen::Enabled
39    }
40}
41#[doc = "Field `CHEN` writer - Channel enable"]
42pub type ChenW<'a, REG> = crate::BitWriter<'a, REG, Chen>;
43impl<'a, REG> ChenW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Channel disabled"]
48    #[inline(always)]
49    pub fn disabled(self) -> &'a mut crate::W<REG> {
50        self.variant(Chen::Disabled)
51    }
52    #[doc = "Channel enabled"]
53    #[inline(always)]
54    pub fn enabled(self) -> &'a mut crate::W<REG> {
55        self.variant(Chen::Enabled)
56    }
57}
58#[doc = "Enable bit for full transfer finish interrupt\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Ftfie {
61    #[doc = "0: Full transfer interrupt disabled"]
62    Disabled = 0,
63    #[doc = "1: Full transfer interrupt enabled"]
64    Enabled = 1,
65}
66impl From<Ftfie> for bool {
67    #[inline(always)]
68    fn from(variant: Ftfie) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `FTFIE` reader - Enable bit for full transfer finish interrupt"]
73pub type FtfieR = crate::BitReader<Ftfie>;
74impl FtfieR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> Ftfie {
78        match self.bits {
79            false => Ftfie::Disabled,
80            true => Ftfie::Enabled,
81        }
82    }
83    #[doc = "Full transfer interrupt disabled"]
84    #[inline(always)]
85    pub fn is_disabled(&self) -> bool {
86        *self == Ftfie::Disabled
87    }
88    #[doc = "Full transfer interrupt enabled"]
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == Ftfie::Enabled
92    }
93}
94#[doc = "Field `FTFIE` writer - Enable bit for full transfer finish interrupt"]
95pub type FtfieW<'a, REG> = crate::BitWriter<'a, REG, Ftfie>;
96impl<'a, REG> FtfieW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Full transfer interrupt disabled"]
101    #[inline(always)]
102    pub fn disabled(self) -> &'a mut crate::W<REG> {
103        self.variant(Ftfie::Disabled)
104    }
105    #[doc = "Full transfer interrupt enabled"]
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(Ftfie::Enabled)
109    }
110}
111#[doc = "Enable bit for half transfer finish interrupt\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum Htfie {
114    #[doc = "0: Half transfer interrupt disabled"]
115    Disabled = 0,
116    #[doc = "1: Half transfer interrupt enabled"]
117    Enabled = 1,
118}
119impl From<Htfie> for bool {
120    #[inline(always)]
121    fn from(variant: Htfie) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `HTFIE` reader - Enable bit for half transfer finish interrupt"]
126pub type HtfieR = crate::BitReader<Htfie>;
127impl HtfieR {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> Htfie {
131        match self.bits {
132            false => Htfie::Disabled,
133            true => Htfie::Enabled,
134        }
135    }
136    #[doc = "Half transfer interrupt disabled"]
137    #[inline(always)]
138    pub fn is_disabled(&self) -> bool {
139        *self == Htfie::Disabled
140    }
141    #[doc = "Half transfer interrupt enabled"]
142    #[inline(always)]
143    pub fn is_enabled(&self) -> bool {
144        *self == Htfie::Enabled
145    }
146}
147#[doc = "Field `HTFIE` writer - Enable bit for half transfer finish interrupt"]
148pub type HtfieW<'a, REG> = crate::BitWriter<'a, REG, Htfie>;
149impl<'a, REG> HtfieW<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Half transfer interrupt disabled"]
154    #[inline(always)]
155    pub fn disabled(self) -> &'a mut crate::W<REG> {
156        self.variant(Htfie::Disabled)
157    }
158    #[doc = "Half transfer interrupt enabled"]
159    #[inline(always)]
160    pub fn enabled(self) -> &'a mut crate::W<REG> {
161        self.variant(Htfie::Enabled)
162    }
163}
164#[doc = "Enable bit for tranfer access error interrupt\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum Errie {
167    #[doc = "0: Transfer error interrupt disabled"]
168    Disabled = 0,
169    #[doc = "1: Transfer error interrupt enabled"]
170    Enabled = 1,
171}
172impl From<Errie> for bool {
173    #[inline(always)]
174    fn from(variant: Errie) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `ERRIE` reader - Enable bit for tranfer access error interrupt"]
179pub type ErrieR = crate::BitReader<Errie>;
180impl ErrieR {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> Errie {
184        match self.bits {
185            false => Errie::Disabled,
186            true => Errie::Enabled,
187        }
188    }
189    #[doc = "Transfer error interrupt disabled"]
190    #[inline(always)]
191    pub fn is_disabled(&self) -> bool {
192        *self == Errie::Disabled
193    }
194    #[doc = "Transfer error interrupt enabled"]
195    #[inline(always)]
196    pub fn is_enabled(&self) -> bool {
197        *self == Errie::Enabled
198    }
199}
200#[doc = "Field `ERRIE` writer - Enable bit for tranfer access error interrupt"]
201pub type ErrieW<'a, REG> = crate::BitWriter<'a, REG, Errie>;
202impl<'a, REG> ErrieW<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Transfer error interrupt disabled"]
207    #[inline(always)]
208    pub fn disabled(self) -> &'a mut crate::W<REG> {
209        self.variant(Errie::Disabled)
210    }
211    #[doc = "Transfer error interrupt enabled"]
212    #[inline(always)]
213    pub fn enabled(self) -> &'a mut crate::W<REG> {
214        self.variant(Errie::Enabled)
215    }
216}
217#[doc = "Transfer mode\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219pub enum Dir {
220    #[doc = "0: Read from peripheral"]
221    FromPeripheral = 0,
222    #[doc = "1: Read from memory"]
223    FromMemory = 1,
224}
225impl From<Dir> for bool {
226    #[inline(always)]
227    fn from(variant: Dir) -> Self {
228        variant as u8 != 0
229    }
230}
231#[doc = "Field `DIR` reader - Transfer mode"]
232pub type DirR = crate::BitReader<Dir>;
233impl DirR {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> Dir {
237        match self.bits {
238            false => Dir::FromPeripheral,
239            true => Dir::FromMemory,
240        }
241    }
242    #[doc = "Read from peripheral"]
243    #[inline(always)]
244    pub fn is_from_peripheral(&self) -> bool {
245        *self == Dir::FromPeripheral
246    }
247    #[doc = "Read from memory"]
248    #[inline(always)]
249    pub fn is_from_memory(&self) -> bool {
250        *self == Dir::FromMemory
251    }
252}
253#[doc = "Field `DIR` writer - Transfer mode"]
254pub type DirW<'a, REG> = crate::BitWriter<'a, REG, Dir>;
255impl<'a, REG> DirW<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "Read from peripheral"]
260    #[inline(always)]
261    pub fn from_peripheral(self) -> &'a mut crate::W<REG> {
262        self.variant(Dir::FromPeripheral)
263    }
264    #[doc = "Read from memory"]
265    #[inline(always)]
266    pub fn from_memory(self) -> &'a mut crate::W<REG> {
267        self.variant(Dir::FromMemory)
268    }
269}
270#[doc = "Circular mode enable\n\nValue on reset: 0"]
271#[derive(Clone, Copy, Debug, PartialEq, Eq)]
272pub enum Cmen {
273    #[doc = "0: Circular buffer disabled"]
274    Disabled = 0,
275    #[doc = "1: Circular buffer enabled"]
276    Enabled = 1,
277}
278impl From<Cmen> for bool {
279    #[inline(always)]
280    fn from(variant: Cmen) -> Self {
281        variant as u8 != 0
282    }
283}
284#[doc = "Field `CMEN` reader - Circular mode enable"]
285pub type CmenR = crate::BitReader<Cmen>;
286impl CmenR {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> Cmen {
290        match self.bits {
291            false => Cmen::Disabled,
292            true => Cmen::Enabled,
293        }
294    }
295    #[doc = "Circular buffer disabled"]
296    #[inline(always)]
297    pub fn is_disabled(&self) -> bool {
298        *self == Cmen::Disabled
299    }
300    #[doc = "Circular buffer enabled"]
301    #[inline(always)]
302    pub fn is_enabled(&self) -> bool {
303        *self == Cmen::Enabled
304    }
305}
306#[doc = "Field `CMEN` writer - Circular mode enable"]
307pub type CmenW<'a, REG> = crate::BitWriter<'a, REG, Cmen>;
308impl<'a, REG> CmenW<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "Circular buffer disabled"]
313    #[inline(always)]
314    pub fn disabled(self) -> &'a mut crate::W<REG> {
315        self.variant(Cmen::Disabled)
316    }
317    #[doc = "Circular buffer enabled"]
318    #[inline(always)]
319    pub fn enabled(self) -> &'a mut crate::W<REG> {
320        self.variant(Cmen::Enabled)
321    }
322}
323#[doc = "Next address generation algorithm of peripheral\n\nValue on reset: 0"]
324#[derive(Clone, Copy, Debug, PartialEq, Eq)]
325pub enum Pnaga {
326    #[doc = "0: Fixed address mode"]
327    Fixed = 0,
328    #[doc = "1: Increment address mode"]
329    Increment = 1,
330}
331impl From<Pnaga> for bool {
332    #[inline(always)]
333    fn from(variant: Pnaga) -> Self {
334        variant as u8 != 0
335    }
336}
337#[doc = "Field `PNAGA` reader - Next address generation algorithm of peripheral"]
338pub type PnagaR = crate::BitReader<Pnaga>;
339impl PnagaR {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> Pnaga {
343        match self.bits {
344            false => Pnaga::Fixed,
345            true => Pnaga::Increment,
346        }
347    }
348    #[doc = "Fixed address mode"]
349    #[inline(always)]
350    pub fn is_fixed(&self) -> bool {
351        *self == Pnaga::Fixed
352    }
353    #[doc = "Increment address mode"]
354    #[inline(always)]
355    pub fn is_increment(&self) -> bool {
356        *self == Pnaga::Increment
357    }
358}
359#[doc = "Field `PNAGA` writer - Next address generation algorithm of peripheral"]
360pub type PnagaW<'a, REG> = crate::BitWriter<'a, REG, Pnaga>;
361impl<'a, REG> PnagaW<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "Fixed address mode"]
366    #[inline(always)]
367    pub fn fixed(self) -> &'a mut crate::W<REG> {
368        self.variant(Pnaga::Fixed)
369    }
370    #[doc = "Increment address mode"]
371    #[inline(always)]
372    pub fn increment(self) -> &'a mut crate::W<REG> {
373        self.variant(Pnaga::Increment)
374    }
375}
376#[doc = "Field `MNAGA` reader - Next address generation algorithm of memory"]
377pub use PnagaR as MnagaR;
378#[doc = "Field `MNAGA` writer - Next address generation algorithm of memory"]
379pub use PnagaW as MnagaW;
380#[doc = "Transfer data size of peripheral\n\nValue on reset: 0"]
381#[derive(Clone, Copy, Debug, PartialEq, Eq)]
382#[repr(u8)]
383pub enum Pwidth {
384    #[doc = "0: 8-bit size"]
385    Bits8 = 0,
386    #[doc = "1: 16-bit size"]
387    Bits16 = 1,
388    #[doc = "2: 32-bit size"]
389    Bits32 = 2,
390}
391impl From<Pwidth> for u8 {
392    #[inline(always)]
393    fn from(variant: Pwidth) -> Self {
394        variant as _
395    }
396}
397impl crate::FieldSpec for Pwidth {
398    type Ux = u8;
399}
400#[doc = "Field `PWIDTH` reader - Transfer data size of peripheral"]
401pub type PwidthR = crate::FieldReader<Pwidth>;
402impl PwidthR {
403    #[doc = "Get enumerated values variant"]
404    #[inline(always)]
405    pub const fn variant(&self) -> Option<Pwidth> {
406        match self.bits {
407            0 => Some(Pwidth::Bits8),
408            1 => Some(Pwidth::Bits16),
409            2 => Some(Pwidth::Bits32),
410            _ => None,
411        }
412    }
413    #[doc = "8-bit size"]
414    #[inline(always)]
415    pub fn is_bits8(&self) -> bool {
416        *self == Pwidth::Bits8
417    }
418    #[doc = "16-bit size"]
419    #[inline(always)]
420    pub fn is_bits16(&self) -> bool {
421        *self == Pwidth::Bits16
422    }
423    #[doc = "32-bit size"]
424    #[inline(always)]
425    pub fn is_bits32(&self) -> bool {
426        *self == Pwidth::Bits32
427    }
428}
429#[doc = "Field `PWIDTH` writer - Transfer data size of peripheral"]
430pub type PwidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwidth>;
431impl<'a, REG> PwidthW<'a, REG>
432where
433    REG: crate::Writable + crate::RegisterSpec,
434    REG::Ux: From<u8>,
435{
436    #[doc = "8-bit size"]
437    #[inline(always)]
438    pub fn bits8(self) -> &'a mut crate::W<REG> {
439        self.variant(Pwidth::Bits8)
440    }
441    #[doc = "16-bit size"]
442    #[inline(always)]
443    pub fn bits16(self) -> &'a mut crate::W<REG> {
444        self.variant(Pwidth::Bits16)
445    }
446    #[doc = "32-bit size"]
447    #[inline(always)]
448    pub fn bits32(self) -> &'a mut crate::W<REG> {
449        self.variant(Pwidth::Bits32)
450    }
451}
452#[doc = "Field `MWIDTH` reader - Transfer data size of memory"]
453pub use PwidthR as MwidthR;
454#[doc = "Field `MWIDTH` writer - Transfer data size of memory"]
455pub use PwidthW as MwidthW;
456#[doc = "Priority Level of this channel\n\nValue on reset: 0"]
457#[derive(Clone, Copy, Debug, PartialEq, Eq)]
458#[repr(u8)]
459pub enum Prio {
460    #[doc = "0: Low priority"]
461    Low = 0,
462    #[doc = "1: Medium priority"]
463    Medium = 1,
464    #[doc = "2: High priority"]
465    High = 2,
466    #[doc = "3: Very high priority"]
467    VeryHigh = 3,
468}
469impl From<Prio> for u8 {
470    #[inline(always)]
471    fn from(variant: Prio) -> Self {
472        variant as _
473    }
474}
475impl crate::FieldSpec for Prio {
476    type Ux = u8;
477}
478#[doc = "Field `PRIO` reader - Priority Level of this channel"]
479pub type PrioR = crate::FieldReader<Prio>;
480impl PrioR {
481    #[doc = "Get enumerated values variant"]
482    #[inline(always)]
483    pub const fn variant(&self) -> Prio {
484        match self.bits {
485            0 => Prio::Low,
486            1 => Prio::Medium,
487            2 => Prio::High,
488            3 => Prio::VeryHigh,
489            _ => unreachable!(),
490        }
491    }
492    #[doc = "Low priority"]
493    #[inline(always)]
494    pub fn is_low(&self) -> bool {
495        *self == Prio::Low
496    }
497    #[doc = "Medium priority"]
498    #[inline(always)]
499    pub fn is_medium(&self) -> bool {
500        *self == Prio::Medium
501    }
502    #[doc = "High priority"]
503    #[inline(always)]
504    pub fn is_high(&self) -> bool {
505        *self == Prio::High
506    }
507    #[doc = "Very high priority"]
508    #[inline(always)]
509    pub fn is_very_high(&self) -> bool {
510        *self == Prio::VeryHigh
511    }
512}
513#[doc = "Field `PRIO` writer - Priority Level of this channel"]
514pub type PrioW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Prio>;
515impl<'a, REG> PrioW<'a, REG>
516where
517    REG: crate::Writable + crate::RegisterSpec,
518    REG::Ux: From<u8>,
519{
520    #[doc = "Low priority"]
521    #[inline(always)]
522    pub fn low(self) -> &'a mut crate::W<REG> {
523        self.variant(Prio::Low)
524    }
525    #[doc = "Medium priority"]
526    #[inline(always)]
527    pub fn medium(self) -> &'a mut crate::W<REG> {
528        self.variant(Prio::Medium)
529    }
530    #[doc = "High priority"]
531    #[inline(always)]
532    pub fn high(self) -> &'a mut crate::W<REG> {
533        self.variant(Prio::High)
534    }
535    #[doc = "Very high priority"]
536    #[inline(always)]
537    pub fn very_high(self) -> &'a mut crate::W<REG> {
538        self.variant(Prio::VeryHigh)
539    }
540}
541#[doc = "Memory to memory mode\n\nValue on reset: 0"]
542#[derive(Clone, Copy, Debug, PartialEq, Eq)]
543pub enum M2m {
544    #[doc = "0: Memory to memory mode disabled"]
545    Disabled = 0,
546    #[doc = "1: Memory to memory mode enabled"]
547    Enabled = 1,
548}
549impl From<M2m> for bool {
550    #[inline(always)]
551    fn from(variant: M2m) -> Self {
552        variant as u8 != 0
553    }
554}
555#[doc = "Field `M2M` reader - Memory to memory mode"]
556pub type M2mR = crate::BitReader<M2m>;
557impl M2mR {
558    #[doc = "Get enumerated values variant"]
559    #[inline(always)]
560    pub const fn variant(&self) -> M2m {
561        match self.bits {
562            false => M2m::Disabled,
563            true => M2m::Enabled,
564        }
565    }
566    #[doc = "Memory to memory mode disabled"]
567    #[inline(always)]
568    pub fn is_disabled(&self) -> bool {
569        *self == M2m::Disabled
570    }
571    #[doc = "Memory to memory mode enabled"]
572    #[inline(always)]
573    pub fn is_enabled(&self) -> bool {
574        *self == M2m::Enabled
575    }
576}
577#[doc = "Field `M2M` writer - Memory to memory mode"]
578pub type M2mW<'a, REG> = crate::BitWriter<'a, REG, M2m>;
579impl<'a, REG> M2mW<'a, REG>
580where
581    REG: crate::Writable + crate::RegisterSpec,
582{
583    #[doc = "Memory to memory mode disabled"]
584    #[inline(always)]
585    pub fn disabled(self) -> &'a mut crate::W<REG> {
586        self.variant(M2m::Disabled)
587    }
588    #[doc = "Memory to memory mode enabled"]
589    #[inline(always)]
590    pub fn enabled(self) -> &'a mut crate::W<REG> {
591        self.variant(M2m::Enabled)
592    }
593}
594impl R {
595    #[doc = "Bit 0 - Channel enable"]
596    #[inline(always)]
597    pub fn chen(&self) -> ChenR {
598        ChenR::new((self.bits & 1) != 0)
599    }
600    #[doc = "Bit 1 - Enable bit for full transfer finish interrupt"]
601    #[inline(always)]
602    pub fn ftfie(&self) -> FtfieR {
603        FtfieR::new(((self.bits >> 1) & 1) != 0)
604    }
605    #[doc = "Bit 2 - Enable bit for half transfer finish interrupt"]
606    #[inline(always)]
607    pub fn htfie(&self) -> HtfieR {
608        HtfieR::new(((self.bits >> 2) & 1) != 0)
609    }
610    #[doc = "Bit 3 - Enable bit for tranfer access error interrupt"]
611    #[inline(always)]
612    pub fn errie(&self) -> ErrieR {
613        ErrieR::new(((self.bits >> 3) & 1) != 0)
614    }
615    #[doc = "Bit 4 - Transfer mode"]
616    #[inline(always)]
617    pub fn dir(&self) -> DirR {
618        DirR::new(((self.bits >> 4) & 1) != 0)
619    }
620    #[doc = "Bit 5 - Circular mode enable"]
621    #[inline(always)]
622    pub fn cmen(&self) -> CmenR {
623        CmenR::new(((self.bits >> 5) & 1) != 0)
624    }
625    #[doc = "Bit 6 - Next address generation algorithm of peripheral"]
626    #[inline(always)]
627    pub fn pnaga(&self) -> PnagaR {
628        PnagaR::new(((self.bits >> 6) & 1) != 0)
629    }
630    #[doc = "Bit 7 - Next address generation algorithm of memory"]
631    #[inline(always)]
632    pub fn mnaga(&self) -> MnagaR {
633        MnagaR::new(((self.bits >> 7) & 1) != 0)
634    }
635    #[doc = "Bits 8:9 - Transfer data size of peripheral"]
636    #[inline(always)]
637    pub fn pwidth(&self) -> PwidthR {
638        PwidthR::new(((self.bits >> 8) & 3) as u8)
639    }
640    #[doc = "Bits 10:11 - Transfer data size of memory"]
641    #[inline(always)]
642    pub fn mwidth(&self) -> MwidthR {
643        MwidthR::new(((self.bits >> 10) & 3) as u8)
644    }
645    #[doc = "Bits 12:13 - Priority Level of this channel"]
646    #[inline(always)]
647    pub fn prio(&self) -> PrioR {
648        PrioR::new(((self.bits >> 12) & 3) as u8)
649    }
650    #[doc = "Bit 14 - Memory to memory mode"]
651    #[inline(always)]
652    pub fn m2m(&self) -> M2mR {
653        M2mR::new(((self.bits >> 14) & 1) != 0)
654    }
655}
656impl W {
657    #[doc = "Bit 0 - Channel enable"]
658    #[inline(always)]
659    #[must_use]
660    pub fn chen(&mut self) -> ChenW<Ch5ctlSpec> {
661        ChenW::new(self, 0)
662    }
663    #[doc = "Bit 1 - Enable bit for full transfer finish interrupt"]
664    #[inline(always)]
665    #[must_use]
666    pub fn ftfie(&mut self) -> FtfieW<Ch5ctlSpec> {
667        FtfieW::new(self, 1)
668    }
669    #[doc = "Bit 2 - Enable bit for half transfer finish interrupt"]
670    #[inline(always)]
671    #[must_use]
672    pub fn htfie(&mut self) -> HtfieW<Ch5ctlSpec> {
673        HtfieW::new(self, 2)
674    }
675    #[doc = "Bit 3 - Enable bit for tranfer access error interrupt"]
676    #[inline(always)]
677    #[must_use]
678    pub fn errie(&mut self) -> ErrieW<Ch5ctlSpec> {
679        ErrieW::new(self, 3)
680    }
681    #[doc = "Bit 4 - Transfer mode"]
682    #[inline(always)]
683    #[must_use]
684    pub fn dir(&mut self) -> DirW<Ch5ctlSpec> {
685        DirW::new(self, 4)
686    }
687    #[doc = "Bit 5 - Circular mode enable"]
688    #[inline(always)]
689    #[must_use]
690    pub fn cmen(&mut self) -> CmenW<Ch5ctlSpec> {
691        CmenW::new(self, 5)
692    }
693    #[doc = "Bit 6 - Next address generation algorithm of peripheral"]
694    #[inline(always)]
695    #[must_use]
696    pub fn pnaga(&mut self) -> PnagaW<Ch5ctlSpec> {
697        PnagaW::new(self, 6)
698    }
699    #[doc = "Bit 7 - Next address generation algorithm of memory"]
700    #[inline(always)]
701    #[must_use]
702    pub fn mnaga(&mut self) -> MnagaW<Ch5ctlSpec> {
703        MnagaW::new(self, 7)
704    }
705    #[doc = "Bits 8:9 - Transfer data size of peripheral"]
706    #[inline(always)]
707    #[must_use]
708    pub fn pwidth(&mut self) -> PwidthW<Ch5ctlSpec> {
709        PwidthW::new(self, 8)
710    }
711    #[doc = "Bits 10:11 - Transfer data size of memory"]
712    #[inline(always)]
713    #[must_use]
714    pub fn mwidth(&mut self) -> MwidthW<Ch5ctlSpec> {
715        MwidthW::new(self, 10)
716    }
717    #[doc = "Bits 12:13 - Priority Level of this channel"]
718    #[inline(always)]
719    #[must_use]
720    pub fn prio(&mut self) -> PrioW<Ch5ctlSpec> {
721        PrioW::new(self, 12)
722    }
723    #[doc = "Bit 14 - Memory to memory mode"]
724    #[inline(always)]
725    #[must_use]
726    pub fn m2m(&mut self) -> M2mW<Ch5ctlSpec> {
727        M2mW::new(self, 14)
728    }
729}
730#[doc = "DMA channel configuration register (DMA_CH5CTL0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch5ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
731pub struct Ch5ctlSpec;
732impl crate::RegisterSpec for Ch5ctlSpec {
733    type Ux = u32;
734}
735#[doc = "`read()` method returns [`ch5ctl::R`](R) reader structure"]
736impl crate::Readable for Ch5ctlSpec {}
737#[doc = "`write(|w| ..)` method takes [`ch5ctl::W`](W) writer structure"]
738impl crate::Writable for Ch5ctlSpec {
739    type Safety = crate::Unsafe;
740    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
741    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
742}
743#[doc = "`reset()` method sets CH5CTL to value 0"]
744impl crate::Resettable for Ch5ctlSpec {
745    const RESET_VALUE: u32 = 0;
746}
gd32f1/gd32f190/dma/ch5ctl.rs

gd32f1/gd32f190/dma/
ch5ctl.rs
