gd32f1/gd32f130/dma/
ch3paddr.rs

1#[doc = "Register `CH3PADDR` reader"]
2pub type R = crate::R<Ch3paddrSpec>;
3#[doc = "Register `CH3PADDR` writer"]
4pub type W = crate::W<Ch3paddrSpec>;
5#[doc = "Field `PADDR` reader - Peripheral base address"]
6pub type PaddrR = crate::FieldReader<u32>;
7#[doc = "Field `PADDR` writer - Peripheral base address"]
8pub type PaddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - Peripheral base address"]
11    #[inline(always)]
12    pub fn paddr(&self) -> PaddrR {
13        PaddrR::new(self.bits)
14    }
15}
16impl W {
17    #[doc = "Bits 0:31 - Peripheral base address"]
18    #[inline(always)]
19    #[must_use]
20    pub fn paddr(&mut self) -> PaddrW<Ch3paddrSpec> {
21        PaddrW::new(self, 0)
22    }
23}
24#[doc = "DMA channel 3 peripheral base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3paddr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3paddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25pub struct Ch3paddrSpec;
26impl crate::RegisterSpec for Ch3paddrSpec {
27    type Ux = u32;
28}
29#[doc = "`read()` method returns [`ch3paddr::R`](R) reader structure"]
30impl crate::Readable for Ch3paddrSpec {}
31#[doc = "`write(|w| ..)` method takes [`ch3paddr::W`](W) writer structure"]
32impl crate::Writable for Ch3paddrSpec {
33    type Safety = crate::Unsafe;
34    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
35    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
36}
37#[doc = "`reset()` method sets CH3PADDR to value 0"]
38impl crate::Resettable for Ch3paddrSpec {
39    const RESET_VALUE: u32 = 0;
40}
gd32f1/gd32f130/dma/ch3paddr.rs

gd32f1/gd32f130/dma/
ch3paddr.rs
