Type Definition gd32f1::gd32f130::rcu::cfg0::W

type W = W<u32, CFG0>;

Writer for register CFG0

Implementations

impl W

pub fn scs(&mut self) -> SCS_W<'_>

Bits 0:1 - System clock switch

pub fn ahbpsc(&mut self) -> AHBPSC_W<'_>

Bits 4:7 - AHB prescaler selection

pub fn apb1psc(&mut self) -> APB1PSC_W<'_>

Bits 8:10 - APB1 prescaler selection

pub fn apb2psc(&mut self) -> APB2PSC_W<'_>

Bits 11:13 - APB2 prescaler selection

pub fn adcpsc(&mut self) -> ADCPSC_W<'_>

Bits 14:15 - ADC clock prescaler selection

pub fn pllsel(&mut self) -> PLLSEL_W<'_>

Bit 16 - PLL Clock Source Selection

pub fn pllpredv(&mut self) -> PLLPREDV_W<'_>

Bit 17 - HXTAL divider for PLL source clock selection.

pub fn pllmf(&mut self) -> PLLMF_W<'_>

Bits 18:21 - PLL multiply factor

pub fn usbdpsc(&mut self) -> USBDPSC_W<'_>

Bits 22:23 - USBD clock prescaler selection

pub fn ckoutsel(&mut self) -> CKOUTSEL_W<'_>

Bits 24:26 - CK_OUT Clock Source Selection

pub fn pllmf_msb(&mut self) -> PLLMF_MSB_W<'_>

Bit 27 - Bit 4 of PLLMF register

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>

Bits 28:30 - The CK_OUT divider which the CK_OUT frequency can be reduced

pub fn plldv(&mut self) -> PLLDV_W<'_>

Bit 31 - The CK_PLL divide by 1 or 2 for CK_OUT