gd32e5/gd32e508/timer10/
chctl0_input.rs

1#[doc = "Register `CHCTL0_Input` reader"]
2pub type R = crate::R<Chctl0InputSpec>;
3#[doc = "Register `CHCTL0_Input` writer"]
4pub type W = crate::W<Chctl0InputSpec>;
5#[doc = "Field `CH0MS` reader - Channel 0 mode selection"]
6pub type Ch0msR = crate::FieldReader;
7#[doc = "Field `CH0MS` writer - Channel 0 mode selection"]
8pub type Ch0msW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `CH0CAPPSC` reader - Channel 0 input capture prescaler"]
10pub type Ch0cappscR = crate::FieldReader;
11#[doc = "Field `CH0CAPPSC` writer - Channel 0 input capture prescaler"]
12pub type Ch0cappscW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `CH0CAPFLT` reader - Channel 0 input capture filter control"]
14pub type Ch0capfltR = crate::FieldReader;
15#[doc = "Field `CH0CAPFLT` writer - Channel 0 input capture filter control"]
16pub type Ch0capfltW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17impl R {
18    #[doc = "Bits 0:1 - Channel 0 mode selection"]
19    #[inline(always)]
20    pub fn ch0ms(&self) -> Ch0msR {
21        Ch0msR::new((self.bits & 3) as u8)
22    }
23    #[doc = "Bits 2:3 - Channel 0 input capture prescaler"]
24    #[inline(always)]
25    pub fn ch0cappsc(&self) -> Ch0cappscR {
26        Ch0cappscR::new(((self.bits >> 2) & 3) as u8)
27    }
28    #[doc = "Bits 4:7 - Channel 0 input capture filter control"]
29    #[inline(always)]
30    pub fn ch0capflt(&self) -> Ch0capfltR {
31        Ch0capfltR::new(((self.bits >> 4) & 0x0f) as u8)
32    }
33}
34impl W {
35    #[doc = "Bits 0:1 - Channel 0 mode selection"]
36    #[inline(always)]
37    #[must_use]
38    pub fn ch0ms(&mut self) -> Ch0msW<Chctl0InputSpec> {
39        Ch0msW::new(self, 0)
40    }
41    #[doc = "Bits 2:3 - Channel 0 input capture prescaler"]
42    #[inline(always)]
43    #[must_use]
44    pub fn ch0cappsc(&mut self) -> Ch0cappscW<Chctl0InputSpec> {
45        Ch0cappscW::new(self, 2)
46    }
47    #[doc = "Bits 4:7 - Channel 0 input capture filter control"]
48    #[inline(always)]
49    #[must_use]
50    pub fn ch0capflt(&mut self) -> Ch0capfltW<Chctl0InputSpec> {
51        Ch0capfltW::new(self, 4)
52    }
53}
54#[doc = "Channel control register 0 ( (input mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctl0_input::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctl0_input::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct Chctl0InputSpec;
56impl crate::RegisterSpec for Chctl0InputSpec {
57    type Ux = u32;
58}
59#[doc = "`read()` method returns [`chctl0_input::R`](R) reader structure"]
60impl crate::Readable for Chctl0InputSpec {}
61#[doc = "`write(|w| ..)` method takes [`chctl0_input::W`](W) writer structure"]
62impl crate::Writable for Chctl0InputSpec {
63    type Safety = crate::Unsafe;
64    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
65    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
66}
67#[doc = "`reset()` method sets CHCTL0_Input to value 0"]
68impl crate::Resettable for Chctl0InputSpec {
69    const RESET_VALUE: u32 = 0;
70}
gd32e5/gd32e508/timer10/chctl0_input.rs

gd32e5/gd32e508/timer10/
chctl0_input.rs
