gd32e5/gd32e508/rcu/
ctl.rs

1#[doc = "Register `CTL` reader"]
2pub type R = crate::R<CtlSpec>;
3#[doc = "Register `CTL` writer"]
4pub type W = crate::W<CtlSpec>;
5#[doc = "Field `IRC8MEN` reader - Internal 8MHz RC oscillator Enable"]
6pub type Irc8menR = crate::BitReader;
7#[doc = "Field `IRC8MEN` writer - Internal 8MHz RC oscillator Enable"]
8pub type Irc8menW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IRC8MSTB` reader - IRC8M Internal 8MHz RC Oscillator stabilization Flag"]
10pub type Irc8mstbR = crate::BitReader;
11#[doc = "Field `IRC8MADJ` reader - Internal 8MHz RC Oscillator clock trim adjust value"]
12pub type Irc8madjR = crate::FieldReader;
13#[doc = "Field `IRC8MADJ` writer - Internal 8MHz RC Oscillator clock trim adjust value"]
14pub type Irc8madjW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
15#[doc = "Field `IRC8MCALIB` reader - Internal 8MHz RC Oscillator calibration value register"]
16pub type Irc8mcalibR = crate::FieldReader;
17#[doc = "Field `HXTALEN` reader - External High Speed oscillator Enable"]
18pub type HxtalenR = crate::BitReader;
19#[doc = "Field `HXTALEN` writer - External High Speed oscillator Enable"]
20pub type HxtalenW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `HXTALSTB` reader - External crystal oscillator (HXTAL) clock stabilization flag"]
22pub type HxtalstbR = crate::BitReader;
23#[doc = "Field `HXTALBPS` reader - External crystal oscillator (HXTAL) clock bypass mode enable"]
24pub type HxtalbpsR = crate::BitReader;
25#[doc = "Field `HXTALBPS` writer - External crystal oscillator (HXTAL) clock bypass mode enable"]
26pub type HxtalbpsW<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `CKMEN` reader - HXTAL Clock Monitor Enable"]
28pub type CkmenR = crate::BitReader;
29#[doc = "Field `CKMEN` writer - HXTAL Clock Monitor Enable"]
30pub type CkmenW<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `PLLEN` reader - PLL enable"]
32pub type PllenR = crate::BitReader;
33#[doc = "Field `PLLEN` writer - PLL enable"]
34pub type PllenW<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `PLLSTB` reader - PLL Clock Stabilization Flag"]
36pub type PllstbR = crate::BitReader;
37#[doc = "Field `PLL1EN` reader - PLL1 enable"]
38pub type Pll1enR = crate::BitReader;
39#[doc = "Field `PLL1EN` writer - PLL1 enable"]
40pub type Pll1enW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `PLL1STB` reader - PLL1 Clock Stabilization Flag"]
42pub type Pll1stbR = crate::BitReader;
43#[doc = "Field `PLL2EN` reader - PLL2 enable"]
44pub type Pll2enR = crate::BitReader;
45#[doc = "Field `PLL2EN` writer - PLL2 enable"]
46pub type Pll2enW<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `PLL2STB` reader - PLL2 Clock Stabilization Flag"]
48pub type Pll2stbR = crate::BitReader;
49impl R {
50    #[doc = "Bit 0 - Internal 8MHz RC oscillator Enable"]
51    #[inline(always)]
52    pub fn irc8men(&self) -> Irc8menR {
53        Irc8menR::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bit 1 - IRC8M Internal 8MHz RC Oscillator stabilization Flag"]
56    #[inline(always)]
57    pub fn irc8mstb(&self) -> Irc8mstbR {
58        Irc8mstbR::new(((self.bits >> 1) & 1) != 0)
59    }
60    #[doc = "Bits 3:7 - Internal 8MHz RC Oscillator clock trim adjust value"]
61    #[inline(always)]
62    pub fn irc8madj(&self) -> Irc8madjR {
63        Irc8madjR::new(((self.bits >> 3) & 0x1f) as u8)
64    }
65    #[doc = "Bits 8:15 - Internal 8MHz RC Oscillator calibration value register"]
66    #[inline(always)]
67    pub fn irc8mcalib(&self) -> Irc8mcalibR {
68        Irc8mcalibR::new(((self.bits >> 8) & 0xff) as u8)
69    }
70    #[doc = "Bit 16 - External High Speed oscillator Enable"]
71    #[inline(always)]
72    pub fn hxtalen(&self) -> HxtalenR {
73        HxtalenR::new(((self.bits >> 16) & 1) != 0)
74    }
75    #[doc = "Bit 17 - External crystal oscillator (HXTAL) clock stabilization flag"]
76    #[inline(always)]
77    pub fn hxtalstb(&self) -> HxtalstbR {
78        HxtalstbR::new(((self.bits >> 17) & 1) != 0)
79    }
80    #[doc = "Bit 18 - External crystal oscillator (HXTAL) clock bypass mode enable"]
81    #[inline(always)]
82    pub fn hxtalbps(&self) -> HxtalbpsR {
83        HxtalbpsR::new(((self.bits >> 18) & 1) != 0)
84    }
85    #[doc = "Bit 19 - HXTAL Clock Monitor Enable"]
86    #[inline(always)]
87    pub fn ckmen(&self) -> CkmenR {
88        CkmenR::new(((self.bits >> 19) & 1) != 0)
89    }
90    #[doc = "Bit 24 - PLL enable"]
91    #[inline(always)]
92    pub fn pllen(&self) -> PllenR {
93        PllenR::new(((self.bits >> 24) & 1) != 0)
94    }
95    #[doc = "Bit 25 - PLL Clock Stabilization Flag"]
96    #[inline(always)]
97    pub fn pllstb(&self) -> PllstbR {
98        PllstbR::new(((self.bits >> 25) & 1) != 0)
99    }
100    #[doc = "Bit 26 - PLL1 enable"]
101    #[inline(always)]
102    pub fn pll1en(&self) -> Pll1enR {
103        Pll1enR::new(((self.bits >> 26) & 1) != 0)
104    }
105    #[doc = "Bit 27 - PLL1 Clock Stabilization Flag"]
106    #[inline(always)]
107    pub fn pll1stb(&self) -> Pll1stbR {
108        Pll1stbR::new(((self.bits >> 27) & 1) != 0)
109    }
110    #[doc = "Bit 28 - PLL2 enable"]
111    #[inline(always)]
112    pub fn pll2en(&self) -> Pll2enR {
113        Pll2enR::new(((self.bits >> 28) & 1) != 0)
114    }
115    #[doc = "Bit 29 - PLL2 Clock Stabilization Flag"]
116    #[inline(always)]
117    pub fn pll2stb(&self) -> Pll2stbR {
118        Pll2stbR::new(((self.bits >> 29) & 1) != 0)
119    }
120}
121impl W {
122    #[doc = "Bit 0 - Internal 8MHz RC oscillator Enable"]
123    #[inline(always)]
124    #[must_use]
125    pub fn irc8men(&mut self) -> Irc8menW<CtlSpec> {
126        Irc8menW::new(self, 0)
127    }
128    #[doc = "Bits 3:7 - Internal 8MHz RC Oscillator clock trim adjust value"]
129    #[inline(always)]
130    #[must_use]
131    pub fn irc8madj(&mut self) -> Irc8madjW<CtlSpec> {
132        Irc8madjW::new(self, 3)
133    }
134    #[doc = "Bit 16 - External High Speed oscillator Enable"]
135    #[inline(always)]
136    #[must_use]
137    pub fn hxtalen(&mut self) -> HxtalenW<CtlSpec> {
138        HxtalenW::new(self, 16)
139    }
140    #[doc = "Bit 18 - External crystal oscillator (HXTAL) clock bypass mode enable"]
141    #[inline(always)]
142    #[must_use]
143    pub fn hxtalbps(&mut self) -> HxtalbpsW<CtlSpec> {
144        HxtalbpsW::new(self, 18)
145    }
146    #[doc = "Bit 19 - HXTAL Clock Monitor Enable"]
147    #[inline(always)]
148    #[must_use]
149    pub fn ckmen(&mut self) -> CkmenW<CtlSpec> {
150        CkmenW::new(self, 19)
151    }
152    #[doc = "Bit 24 - PLL enable"]
153    #[inline(always)]
154    #[must_use]
155    pub fn pllen(&mut self) -> PllenW<CtlSpec> {
156        PllenW::new(self, 24)
157    }
158    #[doc = "Bit 26 - PLL1 enable"]
159    #[inline(always)]
160    #[must_use]
161    pub fn pll1en(&mut self) -> Pll1enW<CtlSpec> {
162        Pll1enW::new(self, 26)
163    }
164    #[doc = "Bit 28 - PLL2 enable"]
165    #[inline(always)]
166    #[must_use]
167    pub fn pll2en(&mut self) -> Pll2enW<CtlSpec> {
168        Pll2enW::new(self, 28)
169    }
170}
171#[doc = "Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
172pub struct CtlSpec;
173impl crate::RegisterSpec for CtlSpec {
174    type Ux = u32;
175}
176#[doc = "`read()` method returns [`ctl::R`](R) reader structure"]
177impl crate::Readable for CtlSpec {}
178#[doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"]
179impl crate::Writable for CtlSpec {
180    type Safety = crate::Unsafe;
181    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
182    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
183}
184#[doc = "`reset()` method sets CTL to value 0x83"]
185impl crate::Resettable for CtlSpec {
186    const RESET_VALUE: u32 = 0x83;
187}
gd32e5/gd32e508/rcu/ctl.rs

gd32e5/gd32e508/rcu/
ctl.rs
