gd32e5/gd32e508/timer1/
intf.rs

1#[doc = "Register `INTF` reader"]
2pub type R = crate::R<IntfSpec>;
3#[doc = "Register `INTF` writer"]
4pub type W = crate::W<IntfSpec>;
5#[doc = "Channel 0 capture/compare interrupt flag"]
6pub use crate::gd32e508::timer0::intf::Ch0if;
7#[doc = "Field `CH0IF` reader - Channel 0 capture/compare interrupt flag"]
8pub use crate::gd32e508::timer0::intf::Ch0ifR;
9#[doc = "Field `CH1IF` reader - Channel 1 capture/compare interrupt flag"]
10pub use crate::gd32e508::timer0::intf::Ch0ifR as Ch1ifR;
11#[doc = "Field `CH2IF` reader - Channel 2 capture/compare interrupt enable"]
12pub use crate::gd32e508::timer0::intf::Ch0ifR as Ch2ifR;
13#[doc = "Field `CH3IF` reader - Channel 3 capture/compare interrupt enable"]
14pub use crate::gd32e508::timer0::intf::Ch0ifR as Ch3ifR;
15#[doc = "Field `CH0IF` writer - Channel 0 capture/compare interrupt flag"]
16pub use crate::gd32e508::timer0::intf::Ch0ifW;
17#[doc = "Field `CH1IF` writer - Channel 1 capture/compare interrupt flag"]
18pub use crate::gd32e508::timer0::intf::Ch0ifW as Ch1ifW;
19#[doc = "Field `CH2IF` writer - Channel 2 capture/compare interrupt enable"]
20pub use crate::gd32e508::timer0::intf::Ch0ifW as Ch2ifW;
21#[doc = "Field `CH3IF` writer - Channel 3 capture/compare interrupt enable"]
22pub use crate::gd32e508::timer0::intf::Ch0ifW as Ch3ifW;
23#[doc = "Update interrupt flag"]
24pub use crate::gd32e508::timer0::intf::Upif;
25#[doc = "Field `UPIF` reader - Update interrupt flag"]
26pub use crate::gd32e508::timer0::intf::UpifR;
27#[doc = "Field `UPIF` writer - Update interrupt flag"]
28pub use crate::gd32e508::timer0::intf::UpifW;
29#[doc = "Trigger interrupt flag\n\nValue on reset: 0"]
30#[derive(Clone, Copy, Debug, PartialEq, Eq)]
31pub enum Trgif {
32    #[doc = "0: No trigger event occured"]
33    Clear = 0,
34    #[doc = "1: Trigger event occurred"]
35    Triggered = 1,
36}
37impl From<Trgif> for bool {
38    #[inline(always)]
39    fn from(variant: Trgif) -> Self {
40        variant as u8 != 0
41    }
42}
43#[doc = "Field `TRGIF` reader - Trigger interrupt flag"]
44pub type TrgifR = crate::BitReader<Trgif>;
45impl TrgifR {
46    #[doc = "Get enumerated values variant"]
47    #[inline(always)]
48    pub const fn variant(&self) -> Trgif {
49        match self.bits {
50            false => Trgif::Clear,
51            true => Trgif::Triggered,
52        }
53    }
54    #[doc = "No trigger event occured"]
55    #[inline(always)]
56    pub fn is_clear(&self) -> bool {
57        *self == Trgif::Clear
58    }
59    #[doc = "Trigger event occurred"]
60    #[inline(always)]
61    pub fn is_triggered(&self) -> bool {
62        *self == Trgif::Triggered
63    }
64}
65#[doc = "Field `TRGIF` writer - Trigger interrupt flag"]
66pub type TrgifW<'a, REG> = crate::BitWriter<'a, REG, Trgif>;
67impl<'a, REG> TrgifW<'a, REG>
68where
69    REG: crate::Writable + crate::RegisterSpec,
70{
71    #[doc = "No trigger event occured"]
72    #[inline(always)]
73    pub fn clear(self) -> &'a mut crate::W<REG> {
74        self.variant(Trgif::Clear)
75    }
76    #[doc = "Trigger event occurred"]
77    #[inline(always)]
78    pub fn triggered(self) -> &'a mut crate::W<REG> {
79        self.variant(Trgif::Triggered)
80    }
81}
82#[doc = "Channel 0 over capture flag"]
83pub use crate::gd32e508::timer0::intf::Ch0of;
84#[doc = "Field `CH0OF` reader - Channel 0 over capture flag"]
85pub use crate::gd32e508::timer0::intf::Ch0ofR;
86#[doc = "Field `CH1OF` reader - Channel 1 over capture flag"]
87pub use crate::gd32e508::timer0::intf::Ch0ofR as Ch1ofR;
88#[doc = "Field `CH2OF` reader - Channel 2 over capture flag"]
89pub use crate::gd32e508::timer0::intf::Ch0ofR as Ch2ofR;
90#[doc = "Field `CH3OF` reader - Channel 3 over capture flag"]
91pub use crate::gd32e508::timer0::intf::Ch0ofR as Ch3ofR;
92#[doc = "Field `CH0OF` writer - Channel 0 over capture flag"]
93pub use crate::gd32e508::timer0::intf::Ch0ofW;
94#[doc = "Field `CH1OF` writer - Channel 1 over capture flag"]
95pub use crate::gd32e508::timer0::intf::Ch0ofW as Ch1ofW;
96#[doc = "Field `CH2OF` writer - Channel 2 over capture flag"]
97pub use crate::gd32e508::timer0::intf::Ch0ofW as Ch2ofW;
98#[doc = "Field `CH3OF` writer - Channel 3 over capture flag"]
99pub use crate::gd32e508::timer0::intf::Ch0ofW as Ch3ofW;
100impl R {
101    #[doc = "Bit 0 - Update interrupt flag"]
102    #[inline(always)]
103    pub fn upif(&self) -> UpifR {
104        UpifR::new((self.bits & 1) != 0)
105    }
106    #[doc = "Bit 1 - Channel 0 capture/compare interrupt flag"]
107    #[inline(always)]
108    pub fn ch0if(&self) -> Ch0ifR {
109        Ch0ifR::new(((self.bits >> 1) & 1) != 0)
110    }
111    #[doc = "Bit 2 - Channel 1 capture/compare interrupt flag"]
112    #[inline(always)]
113    pub fn ch1if(&self) -> Ch1ifR {
114        Ch1ifR::new(((self.bits >> 2) & 1) != 0)
115    }
116    #[doc = "Bit 3 - Channel 2 capture/compare interrupt enable"]
117    #[inline(always)]
118    pub fn ch2if(&self) -> Ch2ifR {
119        Ch2ifR::new(((self.bits >> 3) & 1) != 0)
120    }
121    #[doc = "Bit 4 - Channel 3 capture/compare interrupt enable"]
122    #[inline(always)]
123    pub fn ch3if(&self) -> Ch3ifR {
124        Ch3ifR::new(((self.bits >> 4) & 1) != 0)
125    }
126    #[doc = "Bit 6 - Trigger interrupt flag"]
127    #[inline(always)]
128    pub fn trgif(&self) -> TrgifR {
129        TrgifR::new(((self.bits >> 6) & 1) != 0)
130    }
131    #[doc = "Bit 9 - Channel 0 over capture flag"]
132    #[inline(always)]
133    pub fn ch0of(&self) -> Ch0ofR {
134        Ch0ofR::new(((self.bits >> 9) & 1) != 0)
135    }
136    #[doc = "Bit 10 - Channel 1 over capture flag"]
137    #[inline(always)]
138    pub fn ch1of(&self) -> Ch1ofR {
139        Ch1ofR::new(((self.bits >> 10) & 1) != 0)
140    }
141    #[doc = "Bit 11 - Channel 2 over capture flag"]
142    #[inline(always)]
143    pub fn ch2of(&self) -> Ch2ofR {
144        Ch2ofR::new(((self.bits >> 11) & 1) != 0)
145    }
146    #[doc = "Bit 12 - Channel 3 over capture flag"]
147    #[inline(always)]
148    pub fn ch3of(&self) -> Ch3ofR {
149        Ch3ofR::new(((self.bits >> 12) & 1) != 0)
150    }
151}
152impl W {
153    #[doc = "Bit 0 - Update interrupt flag"]
154    #[inline(always)]
155    #[must_use]
156    pub fn upif(&mut self) -> UpifW<IntfSpec> {
157        UpifW::new(self, 0)
158    }
159    #[doc = "Bit 1 - Channel 0 capture/compare interrupt flag"]
160    #[inline(always)]
161    #[must_use]
162    pub fn ch0if(&mut self) -> Ch0ifW<IntfSpec> {
163        Ch0ifW::new(self, 1)
164    }
165    #[doc = "Bit 2 - Channel 1 capture/compare interrupt flag"]
166    #[inline(always)]
167    #[must_use]
168    pub fn ch1if(&mut self) -> Ch1ifW<IntfSpec> {
169        Ch1ifW::new(self, 2)
170    }
171    #[doc = "Bit 3 - Channel 2 capture/compare interrupt enable"]
172    #[inline(always)]
173    #[must_use]
174    pub fn ch2if(&mut self) -> Ch2ifW<IntfSpec> {
175        Ch2ifW::new(self, 3)
176    }
177    #[doc = "Bit 4 - Channel 3 capture/compare interrupt enable"]
178    #[inline(always)]
179    #[must_use]
180    pub fn ch3if(&mut self) -> Ch3ifW<IntfSpec> {
181        Ch3ifW::new(self, 4)
182    }
183    #[doc = "Bit 6 - Trigger interrupt flag"]
184    #[inline(always)]
185    #[must_use]
186    pub fn trgif(&mut self) -> TrgifW<IntfSpec> {
187        TrgifW::new(self, 6)
188    }
189    #[doc = "Bit 9 - Channel 0 over capture flag"]
190    #[inline(always)]
191    #[must_use]
192    pub fn ch0of(&mut self) -> Ch0ofW<IntfSpec> {
193        Ch0ofW::new(self, 9)
194    }
195    #[doc = "Bit 10 - Channel 1 over capture flag"]
196    #[inline(always)]
197    #[must_use]
198    pub fn ch1of(&mut self) -> Ch1ofW<IntfSpec> {
199        Ch1ofW::new(self, 10)
200    }
201    #[doc = "Bit 11 - Channel 2 over capture flag"]
202    #[inline(always)]
203    #[must_use]
204    pub fn ch2of(&mut self) -> Ch2ofW<IntfSpec> {
205        Ch2ofW::new(self, 11)
206    }
207    #[doc = "Bit 12 - Channel 3 over capture flag"]
208    #[inline(always)]
209    #[must_use]
210    pub fn ch3of(&mut self) -> Ch3ofW<IntfSpec> {
211        Ch3ofW::new(self, 12)
212    }
213}
214#[doc = "interrupt flag register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
215pub struct IntfSpec;
216impl crate::RegisterSpec for IntfSpec {
217    type Ux = u32;
218}
219#[doc = "`read()` method returns [`intf::R`](R) reader structure"]
220impl crate::Readable for IntfSpec {}
221#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"]
222impl crate::Writable for IntfSpec {
223    type Safety = crate::Unsafe;
224    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
225    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
226}
227#[doc = "`reset()` method sets INTF to value 0"]
228impl crate::Resettable for IntfSpec {
229    const RESET_VALUE: u32 = 0;
230}
gd32e5/gd32e508/timer1/intf.rs

gd32e5/gd32e508/timer1/
intf.rs
