gd32e5/gd32e508/spi1/
ctl1.rs

1#[doc = "Register `CTL1` reader"]
2pub type R = crate::R<Ctl1Spec>;
3#[doc = "Register `CTL1` writer"]
4pub type W = crate::W<Ctl1Spec>;
5#[doc = "Rx buffer DMA enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Dmaren {
8    #[doc = "0: Rx buffer DMA disabled"]
9    Disabled = 0,
10    #[doc = "1: Rx buffer DMA enabled"]
11    Enabled = 1,
12}
13impl From<Dmaren> for bool {
14    #[inline(always)]
15    fn from(variant: Dmaren) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `DMAREN` reader - Rx buffer DMA enable"]
20pub type DmarenR = crate::BitReader<Dmaren>;
21impl DmarenR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Dmaren {
25        match self.bits {
26            false => Dmaren::Disabled,
27            true => Dmaren::Enabled,
28        }
29    }
30    #[doc = "Rx buffer DMA disabled"]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == Dmaren::Disabled
34    }
35    #[doc = "Rx buffer DMA enabled"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == Dmaren::Enabled
39    }
40}
41#[doc = "Field `DMAREN` writer - Rx buffer DMA enable"]
42pub type DmarenW<'a, REG> = crate::BitWriter<'a, REG, Dmaren>;
43impl<'a, REG> DmarenW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Rx buffer DMA disabled"]
48    #[inline(always)]
49    pub fn disabled(self) -> &'a mut crate::W<REG> {
50        self.variant(Dmaren::Disabled)
51    }
52    #[doc = "Rx buffer DMA enabled"]
53    #[inline(always)]
54    pub fn enabled(self) -> &'a mut crate::W<REG> {
55        self.variant(Dmaren::Enabled)
56    }
57}
58#[doc = "Transmit Buffer DMA Enable\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Dmaten {
61    #[doc = "0: Tx buffer DMA disabled"]
62    Disabled = 0,
63    #[doc = "1: Tx buffer DMA enabled"]
64    Enabled = 1,
65}
66impl From<Dmaten> for bool {
67    #[inline(always)]
68    fn from(variant: Dmaten) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `DMATEN` reader - Transmit Buffer DMA Enable"]
73pub type DmatenR = crate::BitReader<Dmaten>;
74impl DmatenR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> Dmaten {
78        match self.bits {
79            false => Dmaten::Disabled,
80            true => Dmaten::Enabled,
81        }
82    }
83    #[doc = "Tx buffer DMA disabled"]
84    #[inline(always)]
85    pub fn is_disabled(&self) -> bool {
86        *self == Dmaten::Disabled
87    }
88    #[doc = "Tx buffer DMA enabled"]
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == Dmaten::Enabled
92    }
93}
94#[doc = "Field `DMATEN` writer - Transmit Buffer DMA Enable"]
95pub type DmatenW<'a, REG> = crate::BitWriter<'a, REG, Dmaten>;
96impl<'a, REG> DmatenW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Tx buffer DMA disabled"]
101    #[inline(always)]
102    pub fn disabled(self) -> &'a mut crate::W<REG> {
103        self.variant(Dmaten::Disabled)
104    }
105    #[doc = "Tx buffer DMA enabled"]
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(Dmaten::Enabled)
109    }
110}
111#[doc = "Drive NSS Output\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum Nssdrv {
114    #[doc = "0: NSS output is disabled in master mode"]
115    Disabled = 0,
116    #[doc = "1: NSS output is enabled in master mode"]
117    Enabled = 1,
118}
119impl From<Nssdrv> for bool {
120    #[inline(always)]
121    fn from(variant: Nssdrv) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `NSSDRV` reader - Drive NSS Output"]
126pub type NssdrvR = crate::BitReader<Nssdrv>;
127impl NssdrvR {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> Nssdrv {
131        match self.bits {
132            false => Nssdrv::Disabled,
133            true => Nssdrv::Enabled,
134        }
135    }
136    #[doc = "NSS output is disabled in master mode"]
137    #[inline(always)]
138    pub fn is_disabled(&self) -> bool {
139        *self == Nssdrv::Disabled
140    }
141    #[doc = "NSS output is enabled in master mode"]
142    #[inline(always)]
143    pub fn is_enabled(&self) -> bool {
144        *self == Nssdrv::Enabled
145    }
146}
147#[doc = "Field `NSSDRV` writer - Drive NSS Output"]
148pub type NssdrvW<'a, REG> = crate::BitWriter<'a, REG, Nssdrv>;
149impl<'a, REG> NssdrvW<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "NSS output is disabled in master mode"]
154    #[inline(always)]
155    pub fn disabled(self) -> &'a mut crate::W<REG> {
156        self.variant(Nssdrv::Disabled)
157    }
158    #[doc = "NSS output is enabled in master mode"]
159    #[inline(always)]
160    pub fn enabled(self) -> &'a mut crate::W<REG> {
161        self.variant(Nssdrv::Enabled)
162    }
163}
164#[doc = "Field `NSSP` reader - SPI NSS pulse mode Enable"]
165pub type NsspR = crate::BitReader;
166#[doc = "Field `NSSP` writer - SPI NSS pulse mode Enable"]
167pub type NsspW<'a, REG> = crate::BitWriter<'a, REG>;
168#[doc = "Field `TMOD` reader - SPI TI Mode Enable"]
169pub type TmodR = crate::BitReader;
170#[doc = "Field `TMOD` writer - SPI TI Mode Enable"]
171pub type TmodW<'a, REG> = crate::BitWriter<'a, REG>;
172#[doc = "Error interrupt enable\n\nValue on reset: 0"]
173#[derive(Clone, Copy, Debug, PartialEq, Eq)]
174pub enum Errie {
175    #[doc = "0: Error interrupt disabled"]
176    Disabled = 0,
177    #[doc = "1: Error interrupt enabled"]
178    Enabled = 1,
179}
180impl From<Errie> for bool {
181    #[inline(always)]
182    fn from(variant: Errie) -> Self {
183        variant as u8 != 0
184    }
185}
186#[doc = "Field `ERRIE` reader - Error interrupt enable"]
187pub type ErrieR = crate::BitReader<Errie>;
188impl ErrieR {
189    #[doc = "Get enumerated values variant"]
190    #[inline(always)]
191    pub const fn variant(&self) -> Errie {
192        match self.bits {
193            false => Errie::Disabled,
194            true => Errie::Enabled,
195        }
196    }
197    #[doc = "Error interrupt disabled"]
198    #[inline(always)]
199    pub fn is_disabled(&self) -> bool {
200        *self == Errie::Disabled
201    }
202    #[doc = "Error interrupt enabled"]
203    #[inline(always)]
204    pub fn is_enabled(&self) -> bool {
205        *self == Errie::Enabled
206    }
207}
208#[doc = "Field `ERRIE` writer - Error interrupt enable"]
209pub type ErrieW<'a, REG> = crate::BitWriter<'a, REG, Errie>;
210impl<'a, REG> ErrieW<'a, REG>
211where
212    REG: crate::Writable + crate::RegisterSpec,
213{
214    #[doc = "Error interrupt disabled"]
215    #[inline(always)]
216    pub fn disabled(self) -> &'a mut crate::W<REG> {
217        self.variant(Errie::Disabled)
218    }
219    #[doc = "Error interrupt enabled"]
220    #[inline(always)]
221    pub fn enabled(self) -> &'a mut crate::W<REG> {
222        self.variant(Errie::Enabled)
223    }
224}
225#[doc = "RX buffer not empty interrupt enable\n\nValue on reset: 0"]
226#[derive(Clone, Copy, Debug, PartialEq, Eq)]
227pub enum Rbneie {
228    #[doc = "0: RBNE interrupt disabled"]
229    Disabled = 0,
230    #[doc = "1: RBNE interrupt enabled"]
231    Enabled = 1,
232}
233impl From<Rbneie> for bool {
234    #[inline(always)]
235    fn from(variant: Rbneie) -> Self {
236        variant as u8 != 0
237    }
238}
239#[doc = "Field `RBNEIE` reader - RX buffer not empty interrupt enable"]
240pub type RbneieR = crate::BitReader<Rbneie>;
241impl RbneieR {
242    #[doc = "Get enumerated values variant"]
243    #[inline(always)]
244    pub const fn variant(&self) -> Rbneie {
245        match self.bits {
246            false => Rbneie::Disabled,
247            true => Rbneie::Enabled,
248        }
249    }
250    #[doc = "RBNE interrupt disabled"]
251    #[inline(always)]
252    pub fn is_disabled(&self) -> bool {
253        *self == Rbneie::Disabled
254    }
255    #[doc = "RBNE interrupt enabled"]
256    #[inline(always)]
257    pub fn is_enabled(&self) -> bool {
258        *self == Rbneie::Enabled
259    }
260}
261#[doc = "Field `RBNEIE` writer - RX buffer not empty interrupt enable"]
262pub type RbneieW<'a, REG> = crate::BitWriter<'a, REG, Rbneie>;
263impl<'a, REG> RbneieW<'a, REG>
264where
265    REG: crate::Writable + crate::RegisterSpec,
266{
267    #[doc = "RBNE interrupt disabled"]
268    #[inline(always)]
269    pub fn disabled(self) -> &'a mut crate::W<REG> {
270        self.variant(Rbneie::Disabled)
271    }
272    #[doc = "RBNE interrupt enabled"]
273    #[inline(always)]
274    pub fn enabled(self) -> &'a mut crate::W<REG> {
275        self.variant(Rbneie::Enabled)
276    }
277}
278#[doc = "Tx buffer empty interrupt enable\n\nValue on reset: 0"]
279#[derive(Clone, Copy, Debug, PartialEq, Eq)]
280pub enum Tbeie {
281    #[doc = "0: TBE interrupt disabled"]
282    Disabled = 0,
283    #[doc = "1: TBE interrupt enabled"]
284    Enabled = 1,
285}
286impl From<Tbeie> for bool {
287    #[inline(always)]
288    fn from(variant: Tbeie) -> Self {
289        variant as u8 != 0
290    }
291}
292#[doc = "Field `TBEIE` reader - Tx buffer empty interrupt enable"]
293pub type TbeieR = crate::BitReader<Tbeie>;
294impl TbeieR {
295    #[doc = "Get enumerated values variant"]
296    #[inline(always)]
297    pub const fn variant(&self) -> Tbeie {
298        match self.bits {
299            false => Tbeie::Disabled,
300            true => Tbeie::Enabled,
301        }
302    }
303    #[doc = "TBE interrupt disabled"]
304    #[inline(always)]
305    pub fn is_disabled(&self) -> bool {
306        *self == Tbeie::Disabled
307    }
308    #[doc = "TBE interrupt enabled"]
309    #[inline(always)]
310    pub fn is_enabled(&self) -> bool {
311        *self == Tbeie::Enabled
312    }
313}
314#[doc = "Field `TBEIE` writer - Tx buffer empty interrupt enable"]
315pub type TbeieW<'a, REG> = crate::BitWriter<'a, REG, Tbeie>;
316impl<'a, REG> TbeieW<'a, REG>
317where
318    REG: crate::Writable + crate::RegisterSpec,
319{
320    #[doc = "TBE interrupt disabled"]
321    #[inline(always)]
322    pub fn disabled(self) -> &'a mut crate::W<REG> {
323        self.variant(Tbeie::Disabled)
324    }
325    #[doc = "TBE interrupt enabled"]
326    #[inline(always)]
327    pub fn enabled(self) -> &'a mut crate::W<REG> {
328        self.variant(Tbeie::Enabled)
329    }
330}
331impl R {
332    #[doc = "Bit 0 - Rx buffer DMA enable"]
333    #[inline(always)]
334    pub fn dmaren(&self) -> DmarenR {
335        DmarenR::new((self.bits & 1) != 0)
336    }
337    #[doc = "Bit 1 - Transmit Buffer DMA Enable"]
338    #[inline(always)]
339    pub fn dmaten(&self) -> DmatenR {
340        DmatenR::new(((self.bits >> 1) & 1) != 0)
341    }
342    #[doc = "Bit 2 - Drive NSS Output"]
343    #[inline(always)]
344    pub fn nssdrv(&self) -> NssdrvR {
345        NssdrvR::new(((self.bits >> 2) & 1) != 0)
346    }
347    #[doc = "Bit 3 - SPI NSS pulse mode Enable"]
348    #[inline(always)]
349    pub fn nssp(&self) -> NsspR {
350        NsspR::new(((self.bits >> 3) & 1) != 0)
351    }
352    #[doc = "Bit 4 - SPI TI Mode Enable"]
353    #[inline(always)]
354    pub fn tmod(&self) -> TmodR {
355        TmodR::new(((self.bits >> 4) & 1) != 0)
356    }
357    #[doc = "Bit 5 - Error interrupt enable"]
358    #[inline(always)]
359    pub fn errie(&self) -> ErrieR {
360        ErrieR::new(((self.bits >> 5) & 1) != 0)
361    }
362    #[doc = "Bit 6 - RX buffer not empty interrupt enable"]
363    #[inline(always)]
364    pub fn rbneie(&self) -> RbneieR {
365        RbneieR::new(((self.bits >> 6) & 1) != 0)
366    }
367    #[doc = "Bit 7 - Tx buffer empty interrupt enable"]
368    #[inline(always)]
369    pub fn tbeie(&self) -> TbeieR {
370        TbeieR::new(((self.bits >> 7) & 1) != 0)
371    }
372}
373impl W {
374    #[doc = "Bit 0 - Rx buffer DMA enable"]
375    #[inline(always)]
376    #[must_use]
377    pub fn dmaren(&mut self) -> DmarenW<Ctl1Spec> {
378        DmarenW::new(self, 0)
379    }
380    #[doc = "Bit 1 - Transmit Buffer DMA Enable"]
381    #[inline(always)]
382    #[must_use]
383    pub fn dmaten(&mut self) -> DmatenW<Ctl1Spec> {
384        DmatenW::new(self, 1)
385    }
386    #[doc = "Bit 2 - Drive NSS Output"]
387    #[inline(always)]
388    #[must_use]
389    pub fn nssdrv(&mut self) -> NssdrvW<Ctl1Spec> {
390        NssdrvW::new(self, 2)
391    }
392    #[doc = "Bit 3 - SPI NSS pulse mode Enable"]
393    #[inline(always)]
394    #[must_use]
395    pub fn nssp(&mut self) -> NsspW<Ctl1Spec> {
396        NsspW::new(self, 3)
397    }
398    #[doc = "Bit 4 - SPI TI Mode Enable"]
399    #[inline(always)]
400    #[must_use]
401    pub fn tmod(&mut self) -> TmodW<Ctl1Spec> {
402        TmodW::new(self, 4)
403    }
404    #[doc = "Bit 5 - Error interrupt enable"]
405    #[inline(always)]
406    #[must_use]
407    pub fn errie(&mut self) -> ErrieW<Ctl1Spec> {
408        ErrieW::new(self, 5)
409    }
410    #[doc = "Bit 6 - RX buffer not empty interrupt enable"]
411    #[inline(always)]
412    #[must_use]
413    pub fn rbneie(&mut self) -> RbneieW<Ctl1Spec> {
414        RbneieW::new(self, 6)
415    }
416    #[doc = "Bit 7 - Tx buffer empty interrupt enable"]
417    #[inline(always)]
418    #[must_use]
419    pub fn tbeie(&mut self) -> TbeieW<Ctl1Spec> {
420        TbeieW::new(self, 7)
421    }
422}
423#[doc = "control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
424pub struct Ctl1Spec;
425impl crate::RegisterSpec for Ctl1Spec {
426    type Ux = u32;
427}
428#[doc = "`read()` method returns [`ctl1::R`](R) reader structure"]
429impl crate::Readable for Ctl1Spec {}
430#[doc = "`write(|w| ..)` method takes [`ctl1::W`](W) writer structure"]
431impl crate::Writable for Ctl1Spec {
432    type Safety = crate::Unsafe;
433    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
434    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
435}
436#[doc = "`reset()` method sets CTL1 to value 0"]
437impl crate::Resettable for Ctl1Spec {
438    const RESET_VALUE: u32 = 0;
439}
gd32e5/gd32e508/spi1/ctl1.rs

gd32e5/gd32e508/spi1/
ctl1.rs
