gd32e5/gd32e508/slave_timer0/
st0ch1rst.rs

1#[doc = "Register `ST0CH1RST` reader"]
2pub type R = crate::R<St0ch1rstSpec>;
3#[doc = "Register `ST0CH1RST` writer"]
4pub type W = crate::W<St0ch1rstSpec>;
5#[doc = "Field `CH1RSSEV` reader - Software event generates channel 1"]
6pub type Ch1rssevR = crate::BitReader;
7#[doc = "Field `CH1RSSEV` writer - Software event generates channel 1"]
8pub type Ch1rssevW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CH1RSRST` reader - Slave_TIMER0 reset event generates channel 1"]
10pub type Ch1rsrstR = crate::BitReader;
11#[doc = "Field `CH1RSRST` writer - Slave_TIMER0 reset event generates channel 1"]
12pub type Ch1rsrstW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CH1RSPER` reader - Slave_TIMER0 period event generates channel 1"]
14pub type Ch1rsperR = crate::BitReader;
15#[doc = "Field `CH1RSPER` writer - Slave_TIMER0 period event generates channel 1"]
16pub type Ch1rsperW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CH1RSCMP0` reader - Slave_TIMER0 compare 0 event generates channel 1"]
18pub type Ch1rscmp0R = crate::BitReader;
19#[doc = "Field `CH1RSCMP0` writer - Slave_TIMER0 compare 0 event generates channel 1"]
20pub type Ch1rscmp0W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CH1RSCMP1` reader - Slave_TIMER0 compare 1 event generates channel 1"]
22pub type Ch1rscmp1R = crate::BitReader;
23#[doc = "Field `CH1RSCMP1` writer - Slave_TIMER0 compare 1 event generates channel 1"]
24pub type Ch1rscmp1W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CH1RSCMP2` reader - Slave_TIMER0 compare 2 event generates channel 1"]
26pub type Ch1rscmp2R = crate::BitReader;
27#[doc = "Field `CH1RSCMP2` writer - Slave_TIMER0 compare 2 event generates channel 1"]
28pub type Ch1rscmp2W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CH1RSCMP3` reader - Slave_TIMER0 compare 3 event generates channel 1"]
30pub type Ch1rscmp3R = crate::BitReader;
31#[doc = "Field `CH1RSCMP3` writer - Slave_TIMER0 compare 3 event generates channel 1"]
32pub type Ch1rscmp3W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CH1RSMTPER` reader - Master_TIMER period event generates channel 1"]
34pub type Ch1rsmtperR = crate::BitReader;
35#[doc = "Field `CH1RSMTPER` writer - Master_TIMER period event generates channel 1"]
36pub type Ch1rsmtperW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CH1RSMTCMP0` reader - Master_TIMER compare 0 event generates channel 1"]
38pub type Ch1rsmtcmp0R = crate::BitReader;
39#[doc = "Field `CH1RSMTCMP0` writer - Master_TIMER compare 0 event generates channel 1"]
40pub type Ch1rsmtcmp0W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CH1RSMTCMP1` reader - Master_TIMER compare 1 event generates channel 1"]
42pub type Ch1rsmtcmp1R = crate::BitReader;
43#[doc = "Field `CH1RSMTCMP1` writer - Master_TIMER compare 1 event generates channel 1"]
44pub type Ch1rsmtcmp1W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CH1RSMTCMP2` reader - Master_TIMER compare 2 event generates channel 1"]
46pub type Ch1rsmtcmp2R = crate::BitReader;
47#[doc = "Field `CH1RSMTCMP2` writer - Master_TIMER compare 2 event generates channel 1"]
48pub type Ch1rsmtcmp2W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CH1RSMTCMP3` reader - Master_TIMER compare 3 event generates channel 1"]
50pub type Ch1rsmtcmp3R = crate::BitReader;
51#[doc = "Field `CH1RSMTCMP3` writer - Master_TIMER compare 3 event generates channel 1"]
52pub type Ch1rsmtcmp3W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `CH1RSSTEV0` reader - Slave_TIMER0 interconnection event 0 generates channel 1"]
54pub type Ch1rsstev0R = crate::BitReader;
55#[doc = "Field `CH1RSSTEV0` writer - Slave_TIMER0 interconnection event 0 generates channel 1"]
56pub type Ch1rsstev0W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `CH1RSSTEV1` reader - Slave_TIMER0 interconnection event 1 generates channel 1"]
58pub type Ch1rsstev1R = crate::BitReader;
59#[doc = "Field `CH1RSSTEV1` writer - Slave_TIMER0 interconnection event 1 generates channel 1"]
60pub type Ch1rsstev1W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `CH1RSSTEV2` reader - Slave_TIMER0 interconnection event 2 generates channel 1"]
62pub type Ch1rsstev2R = crate::BitReader;
63#[doc = "Field `CH1RSSTEV2` writer - Slave_TIMER0 interconnection event 2 generates channel 1"]
64pub type Ch1rsstev2W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `CH1RSSTEV3` reader - Slave_TIMER0 interconnection event 3 generates channel 1"]
66pub type Ch1rsstev3R = crate::BitReader;
67#[doc = "Field `CH1RSSTEV3` writer - Slave_TIMER0 interconnection event 3 generates channel 1"]
68pub type Ch1rsstev3W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `CH1RSSTEV4` reader - Slave_TIMER0 interconnection event 4 generates channel 1"]
70pub type Ch1rsstev4R = crate::BitReader;
71#[doc = "Field `CH1RSSTEV4` writer - Slave_TIMER0 interconnection event 4 generates channel 1"]
72pub type Ch1rsstev4W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `CH1RSSTEV5` reader - Slave_TIMER0 interconnection event 5 generates channel 1"]
74pub type Ch1rsstev5R = crate::BitReader;
75#[doc = "Field `CH1RSSTEV5` writer - Slave_TIMER0 interconnection event 5 generates channel 1"]
76pub type Ch1rsstev5W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `CH1RSSTEV6` reader - Slave_TIMER0 interconnection event 6 generates channel 1"]
78pub type Ch1rsstev6R = crate::BitReader;
79#[doc = "Field `CH1RSSTEV6` writer - Slave_TIMER0 interconnection event 6 generates channel 1"]
80pub type Ch1rsstev6W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `CH1RSSTEV7` reader - Slave_TIMER0 interconnection event 7 generates channel 1"]
82pub type Ch1rsstev7R = crate::BitReader;
83#[doc = "Field `CH1RSSTEV7` writer - Slave_TIMER0 interconnection event 7 generates channel 1"]
84pub type Ch1rsstev7W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `CH1RSSTEV8` reader - Slave_TIMER0 interconnection event 8 generates channel 1"]
86pub type Ch1rsstev8R = crate::BitReader;
87#[doc = "Field `CH1RSSTEV8` writer - Slave_TIMER0 interconnection event 8 generates channel 1"]
88pub type Ch1rsstev8W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `CH1RSEXEV0` reader - External event 0 generates channel 1"]
90pub type Ch1rsexev0R = crate::BitReader;
91#[doc = "Field `CH1RSEXEV0` writer - External event 0 generates channel 1"]
92pub type Ch1rsexev0W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `CH1RSEXEV1` reader - External event 1 generates channel 1"]
94pub type Ch1rsexev1R = crate::BitReader;
95#[doc = "Field `CH1RSEXEV1` writer - External event 1 generates channel 1"]
96pub type Ch1rsexev1W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `CH1RSEXEV2` reader - External event 2 generates channel 1"]
98pub type Ch1rsexev2R = crate::BitReader;
99#[doc = "Field `CH1RSEXEV2` writer - External event 2 generates channel 1"]
100pub type Ch1rsexev2W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `CH1RSEXEV3` reader - External event 3 generates channel 1"]
102pub type Ch1rsexev3R = crate::BitReader;
103#[doc = "Field `CH1RSEXEV3` writer - External event 3 generates channel 1"]
104pub type Ch1rsexev3W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `CH1RSEXEV4` reader - External event 4 generates channel 1"]
106pub type Ch1rsexev4R = crate::BitReader;
107#[doc = "Field `CH1RSEXEV4` writer - External event 4 generates channel 1"]
108pub type Ch1rsexev4W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `CH1RSEXEV5` reader - External event 5 generates channel 1"]
110pub type Ch1rsexev5R = crate::BitReader;
111#[doc = "Field `CH1RSEXEV5` writer - External event 5 generates channel 1"]
112pub type Ch1rsexev5W<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `CH1RSEXEV6` reader - External event 6 generates channel 1"]
114pub type Ch1rsexev6R = crate::BitReader;
115#[doc = "Field `CH1RSEXEV6` writer - External event 6 generates channel 1"]
116pub type Ch1rsexev6W<'a, REG> = crate::BitWriter<'a, REG>;
117#[doc = "Field `CH1RSEXEV7` reader - External event 7 generates channel 1"]
118pub type Ch1rsexev7R = crate::BitReader;
119#[doc = "Field `CH1RSEXEV7` writer - External event 7 generates channel 1"]
120pub type Ch1rsexev7W<'a, REG> = crate::BitWriter<'a, REG>;
121#[doc = "Field `CH1RSEXEV8` reader - External event 8 generates channel 1"]
122pub type Ch1rsexev8R = crate::BitReader;
123#[doc = "Field `CH1RSEXEV8` writer - External event 8 generates channel 1"]
124pub type Ch1rsexev8W<'a, REG> = crate::BitWriter<'a, REG>;
125#[doc = "Field `CH1RSEXEV9` reader - External event 9 generates channel 1"]
126pub type Ch1rsexev9R = crate::BitReader;
127#[doc = "Field `CH1RSEXEV9` writer - External event 9 generates channel 1"]
128pub type Ch1rsexev9W<'a, REG> = crate::BitWriter<'a, REG>;
129#[doc = "Field `CH1RSUP` reader - Update event generates channel 1"]
130pub type Ch1rsupR = crate::BitReader;
131#[doc = "Field `CH1RSUP` writer - Update event generates channel 1"]
132pub type Ch1rsupW<'a, REG> = crate::BitWriter<'a, REG>;
133impl R {
134    #[doc = "Bit 0 - Software event generates channel 1"]
135    #[inline(always)]
136    pub fn ch1rssev(&self) -> Ch1rssevR {
137        Ch1rssevR::new((self.bits & 1) != 0)
138    }
139    #[doc = "Bit 1 - Slave_TIMER0 reset event generates channel 1"]
140    #[inline(always)]
141    pub fn ch1rsrst(&self) -> Ch1rsrstR {
142        Ch1rsrstR::new(((self.bits >> 1) & 1) != 0)
143    }
144    #[doc = "Bit 2 - Slave_TIMER0 period event generates channel 1"]
145    #[inline(always)]
146    pub fn ch1rsper(&self) -> Ch1rsperR {
147        Ch1rsperR::new(((self.bits >> 2) & 1) != 0)
148    }
149    #[doc = "Bit 3 - Slave_TIMER0 compare 0 event generates channel 1"]
150    #[inline(always)]
151    pub fn ch1rscmp0(&self) -> Ch1rscmp0R {
152        Ch1rscmp0R::new(((self.bits >> 3) & 1) != 0)
153    }
154    #[doc = "Bit 4 - Slave_TIMER0 compare 1 event generates channel 1"]
155    #[inline(always)]
156    pub fn ch1rscmp1(&self) -> Ch1rscmp1R {
157        Ch1rscmp1R::new(((self.bits >> 4) & 1) != 0)
158    }
159    #[doc = "Bit 5 - Slave_TIMER0 compare 2 event generates channel 1"]
160    #[inline(always)]
161    pub fn ch1rscmp2(&self) -> Ch1rscmp2R {
162        Ch1rscmp2R::new(((self.bits >> 5) & 1) != 0)
163    }
164    #[doc = "Bit 6 - Slave_TIMER0 compare 3 event generates channel 1"]
165    #[inline(always)]
166    pub fn ch1rscmp3(&self) -> Ch1rscmp3R {
167        Ch1rscmp3R::new(((self.bits >> 6) & 1) != 0)
168    }
169    #[doc = "Bit 7 - Master_TIMER period event generates channel 1"]
170    #[inline(always)]
171    pub fn ch1rsmtper(&self) -> Ch1rsmtperR {
172        Ch1rsmtperR::new(((self.bits >> 7) & 1) != 0)
173    }
174    #[doc = "Bit 8 - Master_TIMER compare 0 event generates channel 1"]
175    #[inline(always)]
176    pub fn ch1rsmtcmp0(&self) -> Ch1rsmtcmp0R {
177        Ch1rsmtcmp0R::new(((self.bits >> 8) & 1) != 0)
178    }
179    #[doc = "Bit 9 - Master_TIMER compare 1 event generates channel 1"]
180    #[inline(always)]
181    pub fn ch1rsmtcmp1(&self) -> Ch1rsmtcmp1R {
182        Ch1rsmtcmp1R::new(((self.bits >> 9) & 1) != 0)
183    }
184    #[doc = "Bit 10 - Master_TIMER compare 2 event generates channel 1"]
185    #[inline(always)]
186    pub fn ch1rsmtcmp2(&self) -> Ch1rsmtcmp2R {
187        Ch1rsmtcmp2R::new(((self.bits >> 10) & 1) != 0)
188    }
189    #[doc = "Bit 11 - Master_TIMER compare 3 event generates channel 1"]
190    #[inline(always)]
191    pub fn ch1rsmtcmp3(&self) -> Ch1rsmtcmp3R {
192        Ch1rsmtcmp3R::new(((self.bits >> 11) & 1) != 0)
193    }
194    #[doc = "Bit 12 - Slave_TIMER0 interconnection event 0 generates channel 1"]
195    #[inline(always)]
196    pub fn ch1rsstev0(&self) -> Ch1rsstev0R {
197        Ch1rsstev0R::new(((self.bits >> 12) & 1) != 0)
198    }
199    #[doc = "Bit 13 - Slave_TIMER0 interconnection event 1 generates channel 1"]
200    #[inline(always)]
201    pub fn ch1rsstev1(&self) -> Ch1rsstev1R {
202        Ch1rsstev1R::new(((self.bits >> 13) & 1) != 0)
203    }
204    #[doc = "Bit 14 - Slave_TIMER0 interconnection event 2 generates channel 1"]
205    #[inline(always)]
206    pub fn ch1rsstev2(&self) -> Ch1rsstev2R {
207        Ch1rsstev2R::new(((self.bits >> 14) & 1) != 0)
208    }
209    #[doc = "Bit 15 - Slave_TIMER0 interconnection event 3 generates channel 1"]
210    #[inline(always)]
211    pub fn ch1rsstev3(&self) -> Ch1rsstev3R {
212        Ch1rsstev3R::new(((self.bits >> 15) & 1) != 0)
213    }
214    #[doc = "Bit 16 - Slave_TIMER0 interconnection event 4 generates channel 1"]
215    #[inline(always)]
216    pub fn ch1rsstev4(&self) -> Ch1rsstev4R {
217        Ch1rsstev4R::new(((self.bits >> 16) & 1) != 0)
218    }
219    #[doc = "Bit 17 - Slave_TIMER0 interconnection event 5 generates channel 1"]
220    #[inline(always)]
221    pub fn ch1rsstev5(&self) -> Ch1rsstev5R {
222        Ch1rsstev5R::new(((self.bits >> 17) & 1) != 0)
223    }
224    #[doc = "Bit 18 - Slave_TIMER0 interconnection event 6 generates channel 1"]
225    #[inline(always)]
226    pub fn ch1rsstev6(&self) -> Ch1rsstev6R {
227        Ch1rsstev6R::new(((self.bits >> 18) & 1) != 0)
228    }
229    #[doc = "Bit 19 - Slave_TIMER0 interconnection event 7 generates channel 1"]
230    #[inline(always)]
231    pub fn ch1rsstev7(&self) -> Ch1rsstev7R {
232        Ch1rsstev7R::new(((self.bits >> 19) & 1) != 0)
233    }
234    #[doc = "Bit 20 - Slave_TIMER0 interconnection event 8 generates channel 1"]
235    #[inline(always)]
236    pub fn ch1rsstev8(&self) -> Ch1rsstev8R {
237        Ch1rsstev8R::new(((self.bits >> 20) & 1) != 0)
238    }
239    #[doc = "Bit 21 - External event 0 generates channel 1"]
240    #[inline(always)]
241    pub fn ch1rsexev0(&self) -> Ch1rsexev0R {
242        Ch1rsexev0R::new(((self.bits >> 21) & 1) != 0)
243    }
244    #[doc = "Bit 22 - External event 1 generates channel 1"]
245    #[inline(always)]
246    pub fn ch1rsexev1(&self) -> Ch1rsexev1R {
247        Ch1rsexev1R::new(((self.bits >> 22) & 1) != 0)
248    }
249    #[doc = "Bit 23 - External event 2 generates channel 1"]
250    #[inline(always)]
251    pub fn ch1rsexev2(&self) -> Ch1rsexev2R {
252        Ch1rsexev2R::new(((self.bits >> 23) & 1) != 0)
253    }
254    #[doc = "Bit 24 - External event 3 generates channel 1"]
255    #[inline(always)]
256    pub fn ch1rsexev3(&self) -> Ch1rsexev3R {
257        Ch1rsexev3R::new(((self.bits >> 24) & 1) != 0)
258    }
259    #[doc = "Bit 25 - External event 4 generates channel 1"]
260    #[inline(always)]
261    pub fn ch1rsexev4(&self) -> Ch1rsexev4R {
262        Ch1rsexev4R::new(((self.bits >> 25) & 1) != 0)
263    }
264    #[doc = "Bit 26 - External event 5 generates channel 1"]
265    #[inline(always)]
266    pub fn ch1rsexev5(&self) -> Ch1rsexev5R {
267        Ch1rsexev5R::new(((self.bits >> 26) & 1) != 0)
268    }
269    #[doc = "Bit 27 - External event 6 generates channel 1"]
270    #[inline(always)]
271    pub fn ch1rsexev6(&self) -> Ch1rsexev6R {
272        Ch1rsexev6R::new(((self.bits >> 27) & 1) != 0)
273    }
274    #[doc = "Bit 28 - External event 7 generates channel 1"]
275    #[inline(always)]
276    pub fn ch1rsexev7(&self) -> Ch1rsexev7R {
277        Ch1rsexev7R::new(((self.bits >> 28) & 1) != 0)
278    }
279    #[doc = "Bit 29 - External event 8 generates channel 1"]
280    #[inline(always)]
281    pub fn ch1rsexev8(&self) -> Ch1rsexev8R {
282        Ch1rsexev8R::new(((self.bits >> 29) & 1) != 0)
283    }
284    #[doc = "Bit 30 - External event 9 generates channel 1"]
285    #[inline(always)]
286    pub fn ch1rsexev9(&self) -> Ch1rsexev9R {
287        Ch1rsexev9R::new(((self.bits >> 30) & 1) != 0)
288    }
289    #[doc = "Bit 31 - Update event generates channel 1"]
290    #[inline(always)]
291    pub fn ch1rsup(&self) -> Ch1rsupR {
292        Ch1rsupR::new(((self.bits >> 31) & 1) != 0)
293    }
294}
295impl W {
296    #[doc = "Bit 0 - Software event generates channel 1"]
297    #[inline(always)]
298    #[must_use]
299    pub fn ch1rssev(&mut self) -> Ch1rssevW<St0ch1rstSpec> {
300        Ch1rssevW::new(self, 0)
301    }
302    #[doc = "Bit 1 - Slave_TIMER0 reset event generates channel 1"]
303    #[inline(always)]
304    #[must_use]
305    pub fn ch1rsrst(&mut self) -> Ch1rsrstW<St0ch1rstSpec> {
306        Ch1rsrstW::new(self, 1)
307    }
308    #[doc = "Bit 2 - Slave_TIMER0 period event generates channel 1"]
309    #[inline(always)]
310    #[must_use]
311    pub fn ch1rsper(&mut self) -> Ch1rsperW<St0ch1rstSpec> {
312        Ch1rsperW::new(self, 2)
313    }
314    #[doc = "Bit 3 - Slave_TIMER0 compare 0 event generates channel 1"]
315    #[inline(always)]
316    #[must_use]
317    pub fn ch1rscmp0(&mut self) -> Ch1rscmp0W<St0ch1rstSpec> {
318        Ch1rscmp0W::new(self, 3)
319    }
320    #[doc = "Bit 4 - Slave_TIMER0 compare 1 event generates channel 1"]
321    #[inline(always)]
322    #[must_use]
323    pub fn ch1rscmp1(&mut self) -> Ch1rscmp1W<St0ch1rstSpec> {
324        Ch1rscmp1W::new(self, 4)
325    }
326    #[doc = "Bit 5 - Slave_TIMER0 compare 2 event generates channel 1"]
327    #[inline(always)]
328    #[must_use]
329    pub fn ch1rscmp2(&mut self) -> Ch1rscmp2W<St0ch1rstSpec> {
330        Ch1rscmp2W::new(self, 5)
331    }
332    #[doc = "Bit 6 - Slave_TIMER0 compare 3 event generates channel 1"]
333    #[inline(always)]
334    #[must_use]
335    pub fn ch1rscmp3(&mut self) -> Ch1rscmp3W<St0ch1rstSpec> {
336        Ch1rscmp3W::new(self, 6)
337    }
338    #[doc = "Bit 7 - Master_TIMER period event generates channel 1"]
339    #[inline(always)]
340    #[must_use]
341    pub fn ch1rsmtper(&mut self) -> Ch1rsmtperW<St0ch1rstSpec> {
342        Ch1rsmtperW::new(self, 7)
343    }
344    #[doc = "Bit 8 - Master_TIMER compare 0 event generates channel 1"]
345    #[inline(always)]
346    #[must_use]
347    pub fn ch1rsmtcmp0(&mut self) -> Ch1rsmtcmp0W<St0ch1rstSpec> {
348        Ch1rsmtcmp0W::new(self, 8)
349    }
350    #[doc = "Bit 9 - Master_TIMER compare 1 event generates channel 1"]
351    #[inline(always)]
352    #[must_use]
353    pub fn ch1rsmtcmp1(&mut self) -> Ch1rsmtcmp1W<St0ch1rstSpec> {
354        Ch1rsmtcmp1W::new(self, 9)
355    }
356    #[doc = "Bit 10 - Master_TIMER compare 2 event generates channel 1"]
357    #[inline(always)]
358    #[must_use]
359    pub fn ch1rsmtcmp2(&mut self) -> Ch1rsmtcmp2W<St0ch1rstSpec> {
360        Ch1rsmtcmp2W::new(self, 10)
361    }
362    #[doc = "Bit 11 - Master_TIMER compare 3 event generates channel 1"]
363    #[inline(always)]
364    #[must_use]
365    pub fn ch1rsmtcmp3(&mut self) -> Ch1rsmtcmp3W<St0ch1rstSpec> {
366        Ch1rsmtcmp3W::new(self, 11)
367    }
368    #[doc = "Bit 12 - Slave_TIMER0 interconnection event 0 generates channel 1"]
369    #[inline(always)]
370    #[must_use]
371    pub fn ch1rsstev0(&mut self) -> Ch1rsstev0W<St0ch1rstSpec> {
372        Ch1rsstev0W::new(self, 12)
373    }
374    #[doc = "Bit 13 - Slave_TIMER0 interconnection event 1 generates channel 1"]
375    #[inline(always)]
376    #[must_use]
377    pub fn ch1rsstev1(&mut self) -> Ch1rsstev1W<St0ch1rstSpec> {
378        Ch1rsstev1W::new(self, 13)
379    }
380    #[doc = "Bit 14 - Slave_TIMER0 interconnection event 2 generates channel 1"]
381    #[inline(always)]
382    #[must_use]
383    pub fn ch1rsstev2(&mut self) -> Ch1rsstev2W<St0ch1rstSpec> {
384        Ch1rsstev2W::new(self, 14)
385    }
386    #[doc = "Bit 15 - Slave_TIMER0 interconnection event 3 generates channel 1"]
387    #[inline(always)]
388    #[must_use]
389    pub fn ch1rsstev3(&mut self) -> Ch1rsstev3W<St0ch1rstSpec> {
390        Ch1rsstev3W::new(self, 15)
391    }
392    #[doc = "Bit 16 - Slave_TIMER0 interconnection event 4 generates channel 1"]
393    #[inline(always)]
394    #[must_use]
395    pub fn ch1rsstev4(&mut self) -> Ch1rsstev4W<St0ch1rstSpec> {
396        Ch1rsstev4W::new(self, 16)
397    }
398    #[doc = "Bit 17 - Slave_TIMER0 interconnection event 5 generates channel 1"]
399    #[inline(always)]
400    #[must_use]
401    pub fn ch1rsstev5(&mut self) -> Ch1rsstev5W<St0ch1rstSpec> {
402        Ch1rsstev5W::new(self, 17)
403    }
404    #[doc = "Bit 18 - Slave_TIMER0 interconnection event 6 generates channel 1"]
405    #[inline(always)]
406    #[must_use]
407    pub fn ch1rsstev6(&mut self) -> Ch1rsstev6W<St0ch1rstSpec> {
408        Ch1rsstev6W::new(self, 18)
409    }
410    #[doc = "Bit 19 - Slave_TIMER0 interconnection event 7 generates channel 1"]
411    #[inline(always)]
412    #[must_use]
413    pub fn ch1rsstev7(&mut self) -> Ch1rsstev7W<St0ch1rstSpec> {
414        Ch1rsstev7W::new(self, 19)
415    }
416    #[doc = "Bit 20 - Slave_TIMER0 interconnection event 8 generates channel 1"]
417    #[inline(always)]
418    #[must_use]
419    pub fn ch1rsstev8(&mut self) -> Ch1rsstev8W<St0ch1rstSpec> {
420        Ch1rsstev8W::new(self, 20)
421    }
422    #[doc = "Bit 21 - External event 0 generates channel 1"]
423    #[inline(always)]
424    #[must_use]
425    pub fn ch1rsexev0(&mut self) -> Ch1rsexev0W<St0ch1rstSpec> {
426        Ch1rsexev0W::new(self, 21)
427    }
428    #[doc = "Bit 22 - External event 1 generates channel 1"]
429    #[inline(always)]
430    #[must_use]
431    pub fn ch1rsexev1(&mut self) -> Ch1rsexev1W<St0ch1rstSpec> {
432        Ch1rsexev1W::new(self, 22)
433    }
434    #[doc = "Bit 23 - External event 2 generates channel 1"]
435    #[inline(always)]
436    #[must_use]
437    pub fn ch1rsexev2(&mut self) -> Ch1rsexev2W<St0ch1rstSpec> {
438        Ch1rsexev2W::new(self, 23)
439    }
440    #[doc = "Bit 24 - External event 3 generates channel 1"]
441    #[inline(always)]
442    #[must_use]
443    pub fn ch1rsexev3(&mut self) -> Ch1rsexev3W<St0ch1rstSpec> {
444        Ch1rsexev3W::new(self, 24)
445    }
446    #[doc = "Bit 25 - External event 4 generates channel 1"]
447    #[inline(always)]
448    #[must_use]
449    pub fn ch1rsexev4(&mut self) -> Ch1rsexev4W<St0ch1rstSpec> {
450        Ch1rsexev4W::new(self, 25)
451    }
452    #[doc = "Bit 26 - External event 5 generates channel 1"]
453    #[inline(always)]
454    #[must_use]
455    pub fn ch1rsexev5(&mut self) -> Ch1rsexev5W<St0ch1rstSpec> {
456        Ch1rsexev5W::new(self, 26)
457    }
458    #[doc = "Bit 27 - External event 6 generates channel 1"]
459    #[inline(always)]
460    #[must_use]
461    pub fn ch1rsexev6(&mut self) -> Ch1rsexev6W<St0ch1rstSpec> {
462        Ch1rsexev6W::new(self, 27)
463    }
464    #[doc = "Bit 28 - External event 7 generates channel 1"]
465    #[inline(always)]
466    #[must_use]
467    pub fn ch1rsexev7(&mut self) -> Ch1rsexev7W<St0ch1rstSpec> {
468        Ch1rsexev7W::new(self, 28)
469    }
470    #[doc = "Bit 29 - External event 8 generates channel 1"]
471    #[inline(always)]
472    #[must_use]
473    pub fn ch1rsexev8(&mut self) -> Ch1rsexev8W<St0ch1rstSpec> {
474        Ch1rsexev8W::new(self, 29)
475    }
476    #[doc = "Bit 30 - External event 9 generates channel 1"]
477    #[inline(always)]
478    #[must_use]
479    pub fn ch1rsexev9(&mut self) -> Ch1rsexev9W<St0ch1rstSpec> {
480        Ch1rsexev9W::new(self, 30)
481    }
482    #[doc = "Bit 31 - Update event generates channel 1"]
483    #[inline(always)]
484    #[must_use]
485    pub fn ch1rsup(&mut self) -> Ch1rsupW<St0ch1rstSpec> {
486        Ch1rsupW::new(self, 31)
487    }
488}
489#[doc = "SHRTIMER Slave_TIMER0 channel 1 reset request register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st0ch1rst::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st0ch1rst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
490pub struct St0ch1rstSpec;
491impl crate::RegisterSpec for St0ch1rstSpec {
492    type Ux = u32;
493}
494#[doc = "`read()` method returns [`st0ch1rst::R`](R) reader structure"]
495impl crate::Readable for St0ch1rstSpec {}
496#[doc = "`write(|w| ..)` method takes [`st0ch1rst::W`](W) writer structure"]
497impl crate::Writable for St0ch1rstSpec {
498    type Safety = crate::Unsafe;
499    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
500    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
501}
502#[doc = "`reset()` method sets ST0CH1RST to value 0"]
503impl crate::Resettable for St0ch1rstSpec {
504    const RESET_VALUE: u32 = 0;
505}
gd32e5/gd32e508/slave_timer0/st0ch1rst.rs

gd32e5/gd32e508/slave_timer0/
st0ch1rst.rs
